VLSI Architecture Design For Spiking Convolutional Neural Network

In recent years,Artificial Neural Networks(ANN)have become a hot issue in the field of artificial intelligence.Among them,convolutional neural network(CNN)is currently the fastest growing neural network.However,the CNN has high computa-tional operations and large computational complexity,resulting in large hardware en-ergy consumption.As another branch of the neural network,spiking neural network(SNN)uses spiking signals to transmit information,reduce the amount of network op-erations and greatly improve energy efficiency.But the accuracy of SNN is low.The spiking convolutional neural network combines the high-accuracy feature of CNN and high-energy-efficiency feature of SNN which is developed recently.Memristor is an emerging device that has emerged in recent years.Resistive Random Access Memory(ReRAM)is used by many scholars for neuromorphic circuit design due to the non-volatile,high-frequency reading-and-writing properties.ReRAM is a promising future device.The main research content of this thesis is the ReRAM/CMOS hybrid hardware accelerator design of spiking CNN.A configurable VLSI spiking processing array is built.The article mainly includes the following aspects:Spiking Convolutional Neural Network Model Construction:One way is to con-vert the weights of the CNNs into the weights of the neurons in the SNNs.This thesis proposes a normalization algorithm based on Monte Carlo Method.Compared with the traditional normalization algorithm,for the LeNet-5 network,when the optimization tar-get is delay,the SCNN's delay can be reduced with an accuracy of 98.04%by 42.3%.When the optimization target is accuracy,the accuracy can be as high as 98.39%.Specific spiking convolutional neural network accelerator architecture:According to the structure of LeNet-5,we design data flow path and control flow path,and build a pipeline digital circuit to deal with corresponding SCNN.The data path includes specific neuron processing circuit and data buffering circuit between the layers.The specific neuron processing circuit consists of a distributed storage weight module,an addition tree,a spiking firing and a membrane potential reset module.Compared with the CNN which has the same topology,the energy consumed by SCNN reduces about 50%when processes the MNIST dataset.Configurable Pulsation Processing Array VLSI Architecture:This thesis proposes a configurable spiking processing array.In the array,a column of CBUs can be con-figured as spiking neurons corresponding to convolutional kernels with various sizes while the whole array can be configured to provide row parallelism for a kernel con-volution and inter-kernel parallelism when process input images.The array consists of an input and output module,a scheduler module,and an array of processing units.The processing unit is a hybrid circuit based on ReRAM/CMOS,the CMOS circuit part performs neuron membrane potential operation and spiking firing operation,and the ReRAM circuit part is storing neuron synaptic weights.Using the MNIST data set for power consumption testing,compared with the conventional CPU,GPU and other general-purpose processors,the energy consumption of the processing array proposed in this thesis can be reduced by more than two orders of magnitude.Compared with the advanced architecture based on ReRAM,the energy consumption in our design is lower than an order of magnitude.