| Convolutional neural networks are widely used because of their unique characteristics.With the pursuit of the accuracy of convolutional neural network models,network models are also developing under a deeper and more complex architecture,which requires the deployment platform to match it.hardware conditions and resource overhead.This also brings greater challenges to subsequent model deployment,so the lightweight of convolutional neural networks is an important research direction of convolutional neural networks in recent years.In the past,platforms equipped with neural networks,such as central processing units(CPUs)and graphics processing units(GPUs),used a large number of floating-point arithmetic units to accelerate convolution operations.Power consumption and expensive hardware resources also bring problems such as inability to deploy on platforms with limited resource overhead such as embedded.As a convolutional neural network carrying platform in recent years,FPGA is more suitable for the construction of convolutional neural network than general-purpose processors due to its rich computing resources and design reconfigurability.Combined with network model lightweighting and other methods,FPGA can reduce the data volume and computing resource consumption of the model without sacrificing the accuracy of the model too much,providing a solution for deploying deep convolutional neural networks in server clusters or embedded environments.a possibility.To sum up,the main work of this paper is as follows:1.Aiming at the problem of lightweight network model,a backbone extraction network based on deep separation convolution is proposed,which is used to reduce the amount of parameters of the network and further compress the network size to achieve the purpose of network lightweighting.2.Aiming at the problem that the network model is too large and it is difficult to deploy the FPGA platform,a lightweight convolutional neural network YOLO-Shuffle Net-tiny is proposed,and the model is further compressed with the idea of data quantification so that it can be deployed on the FPGA platform.3.Aiming at the problem that the hardware acceleration of the model occupies too much hardware resources,a hardware acceleration method is proposed,and the hardware acceleration of each module is optimized by using the GEMM algorithm,etc.and the vectorization and deformation of the organization form of the data reduces the operation time and further reduces the data storage pressure.And for the above methods of software system design research. |
