| With the rapid development of modern electronic information technology represented by cloud computing and the Internet of Things,the requirements for intelligent terminals are increasing day by day.As the core of intelligent terminals,MGU(microcontroller unit)also bears an increasing pressure on data throughput.For many applications,the MCU cannot be completely relied on for real-time data processing.For scenarios that need to process a large number of fixed operator operations and require low latency and instant response,adding commonly used operator hardware accelerators to MCU is an effective means to implement low-cost,high-performance embedded systems,and has good engineering application prospects.With the development of integrated circuits,the research of hardware accelerators in the field of integrated circuits has always been a hot and difficult point.Similarly,it is also of great significance in practical application.This thesis focuses on the hardwareization of five commonly used vector operators(compare operator,average operator,subtraction operator,copy operator and list operator),the high-speed read and write operations of modules to memory,and the vector accelerator is verified by building a UVM(Universal Verification Methodology)verification platform.The research on high-performance hardware vector accelerators includes the following aspects:(1)Study the Advanced Hihg Performance Bus and ICB(Internal Chip Bus)bus,analyze the functional characteristics of the vector accelerator,draw a design block diagram,design the internal modules of the vector accelerator,and connect the signals of the internal memory reading module,memory writing module,arbitration processing module,hardware acceleration unit module,operand buffer module,data format conversion module,received data buffer module and register module,A complete high-performance hardware vector accelerator is designed.(2)Research high-performance hardware vector accelerators for high-speed input and output data read and write operations of compare operators,average operators,subtraction operators,copy operators and list operators,which can support byte,half-word,and word data.Read and write,support the processing of signed and unsigned data,and support the reading and storage of big-endian and little-endian.(3)Study UVM verification methodology and learn the knowledge of UVM’s phase mechanism,objection mechanism,sequence mechanism,field automation mechanism,config_db mechanism,factory mechanism,TLM(Transaction Level Modeling)mechanism and register model.Complete the design of vector accelerator automatic verification platform guided by code coverage and function coverage.(4)Extract verification function points according to the functional characteristics of high-performance hardware vector accelerators,write test cases and functional coverage models,and implement automatic regression testing through perl scripts and makefile scripts.Use the XCELIUM1909 tool provided by Cadence to compile and simulate,run the test case,view the simulation waveform through verdi,and use the IMC tool to collect coverage,achieve 100%code and functional coverage,and confirm that the functional verification of the vector accelerator module meets the requirements,to achieve the desired goal. |
