Design And Implementation Of IoT Processor Based On RISC-V Architecture

With the continued popularity of the Internet of Things and artificial intelligence industry,it is foreseeable that tens of thousands of smart devices will be connected to the network in the future,which will promote the consumption of a large number of IoT processor chips and drive the development of the integrated circuit industry.The main task of IoT devices is to collect node information and personalized edge computing.Therefore,low power consumption and customized computing requirements are the key to IoT technology.However,general-purpose processors on the market often have poor scalability and difficult to control power consumption,which can no longer meet increasingly complex IoT applications.Therefore,it has important practical significance to develop an IoT processor based on RISC-V architecture for IoT applications.Through the analysis of different application scenarios of the Internet of Things processor,the processor adopts the RISC-V instruction set,supports multiplication and atomic instruction expansion,and the core adopts a three-stage pipeline design for fetching,decoding,and execution,which is divided into the Frontend and the Core modules.The Frontend module is responsible for fetching instruction and PC generation,and the Core module is responsible for computing and writing back.The processor is equipped with instruction and data tightly coupled memory,and adopts a multi-level memory design.It caches instructions and data from Flash to tightly coupled memory when booting up,and jumps to tightly coupled memory to execute programs,which effectively improves processor performance and reduced hardware complexity.In the design of the bus,we simplified the Diplomacy mechanism of the RocketChip project and built a unique bus negotiation model,compatible with the TileLink bus and a large number of open source IP,so that we can always focus on processor research.And the design adopts multi-level verification such as Chisel model and FPGA prototype,and finally implements the back-end implementation of the processor based on SMIC’s 180nm process.The results show that the frequency of the processor can reach 50MHz,the area of the processor circuit is only 0.37mm2,and the average power consumption is 0.042mW/MHz.This article uses the agile development language Chisel for hardware development.The test set uses the official instruction set test cases RV32I,RV32M and RV32A,and evaluates the performance of the processor through the classic test program.The evaluation result is the Dhrystone score of 1.03 DMIPS/MHz,the CoreMark score of 2.72 CoreMarks/MHz.