Research And Design Of Low Power Harmonic Rejection Transmitter Chip

With the advancement of science and the development of medical technology,more and more wearable and implantable wireless communication devices have been applied to the auxiliary medical field,which promotes the modernization and intelli-gence of the medical system.The transmitter is an indispensable part of the wireless communication system,and its performance is very important.Medical device shows high requirements on the power consumption and area of the transmitter chip.Trans-mitters typically rely on bulky on/off chip filters to remove the harmonics.As a result,it is important to study the transmitter with harmonic rejection function.This thesis proposes a new transmitter architecture with harmonic rejection for low power medical applications.Based on this architecture,two low power harmonic rejection transmitter chips are designed.The main contents are as follows:（1）From the system point of view,a harmonic rejection edge combination trans-mitter architecture based on delay-locked loop is proposed.The harmonic rejection technology is integrated with the frequency multiplication circuit,and the signal wave-form is synthesized to suppress the 3^rd/5^th harmonics while achieving the frequency multiplication.As a result,the system relaxes the requirements for on/off chip filters and reduces the area of the chip.The architecture utilizes a delay-locked loop as the clock generation module,which shows the advantages of small area,less noise accu-mulation,and better stability.To save the total power consumption,the frequency mul-tiplication technology ensures that the clock generation circuit and the data modulation circuit can work at low frequency.（2）A harmonic rejection edge combiner based on capacitive coupling is designed.According to the charge addition characteristic of capacitor and the frequency multipli-cation characteristic of edge combiner,three groups of low-frequency square-wave sig-nals are multiplied and weighted together to synthesize the high frequency signal with the function of suppressing 3^rd-/5^th-order harmonics.The chip is designed with a 65 nm CMOS SOI technology.The post-simulation results show that the transmitter can achieve more than 3^rd-order harmonic rejection of 45d Bc and 5^th-order harmonic rejec-tion of 54d Bc in the frequency range of 401-406 MHz、413-419 MHz、426-432 MHz、438-444 MHz and 451-457 MHz Med Radio band and 433.05-434.79 MHz ISM band.The output power is greater than-6.5 d Bm,the power consumption is less than 1.4 m W,and the core area is 0.03 mm².（3）A harmonic rejection edge combiner based on resistor divider is also designed.The series-parallel combination of resistors can achieve different voltage division states,thereby synthesizing high-frequency step-wave with 3^rd-/5^th-order harmonics rejection.The chip is also designed with a 65 nm CMOS SOI technology.The post-simulation results show that the transmitter can support 401-406 MHz,413-419 MHz,426-432MHz,438-444 MHz and 451-457 MHz Med Radio band and 433.05-434.79 MHz ISM band.The 3^rd-/5^th-order harmonic rejection ratios are greater than 40 d Bc and 50 d Bc,respectively,and the output power is greater than-17.9 d Bm.The overall power con-sumption including the driver stage is less than 1.5 m W,and the power consumption without the driver stage is about 800μW,and the core area is 0.05 mm².