Design Of Low Voltage Harmonic-rejection Edge-combining Transmitter

In this thesis,a 433 MHz ISM-band low voltage harmonic-rejection edge-combining transmitter is designed,which can be used in the Internet of Things and biomedical applications.We propose a novel RF transmitter that utilizing charge-pump type bootstrap circuit to boost voltage swing.As a result,the two-stage injection locked ring oscillator,the data modulator and pahse shifter can work well under the supply voltage of 0.6V,and it also can significantly save the tatal power consumption.Meanwhile,we propose a harmonic-rejection edge-combining scheme based on divided resistor,which can avoid the on-or off-chip matching network of the traditional transmitter for area saving.First,a background investigation is performed on the transmitters in the field of Internet of Things and biomedicine,after that,the system architecture of the RF transmitter is proposed and designed including the specifications.Second,three key transmitter technologies is analyzed in detail including injection-locking technology,frequency multiplying technology and harmonic-rejection technology,which provides a theoretical basis for circuit design.Third,the design of two-stage injection locked ring oscillator,data modulator,phase shifter,SPI interface circuit,charge-pump bootstrap circuit and harmonic rejection edge combiner are introduced in detail;Meanwhile,the test results of edge-combining frequency multiplier are given.Finally,this thesis shows the layout design of the low voltage harmonic-rejection edge-combining transmitter and the analysis of post simulation results.The transmitter is designed in 55 nm CMOS process,including circuit-level design,layout design and simulation verification.It can be seen from the simulation results that the transmitter chip designed in this paper can stably output a 433 MHz high-frequency signal by injecting a 48.1MHz reference signal.The signal waveform is similar to a sine wave,and the third-order harmonic-rejection ratio is 29.4d Bc,and the fifth-order harmonic-rejection ratio is38.3d Bc.The whole system uses 0.6V and 1.2V dual voltage power supply,the total power consumption is 634?W,and the output power is-17.7d Bm.The chip area is 381?m×373?m.