A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Application |
Posted on:2017-11-25 | Degree:Master' | Type:Thesis |
University:University of Washington | Candidate:Huang, Chenxi | Full Text:PDF |
GTID:2468390011995462 | Subject:Electrical engineering |
Abstract/Summary: | |
This thesis describes a single-ended switch-capacitor harmonic-rejection power amplifier for the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2 nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180mumx700mum. |
Keywords/Search Tags: | Harmonic-rejection, Power amplifier, Switch-capacitor |
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