Hardware Design Of Lightweight SM2 Algorithm Against Power Analysis Attack

Nowadays,internet of things(IoT)devices are gradually integrated into our lives,making them more comfortable,such as:smart cameras,smart cars,smart robots,etc.However,with the emergence of a great quantity of IoT devices,this provides a lot of eavesdropping opportunities for information attackers,which puts forward stricter requirements on the security of the security chips of IoT devices.Therefore,for the security chip for IoT devices,we first consider the security of the cryptographic algorithm used,then the hardware resource cost of the security chip,and finally the performance of the security chip.When designing,when there is a conflict between security and resources,it is necessary to increase the consumption of hardware resources to meet security;In the event of a conflict between resources and performance,performance must be sacrificed to meet the lightweight requirements.Among the many cryptographic algorithms,the first asymmetric cryptographic algorithm developed by my country,the SM2 cryptographic algorithm,is meeting the above requirements.With the development of cryptographic algorithms,attackers have also emerged in an endless stream of attack methods to decipher security chips to obtain information.Among them,the power consumption analysis attack deciphering the efficiency of the security chip has the greatest threat to the security chip.Therefore,Therefore,the realization of the lightweight level of the SM2 encryption algorithm and the design of the power consumption analysis capability have large propulsion in the development of the IoT.This thesis analyzes the public key generation in SM2 cryptographic algorithm,that is,the point multiplication operation on elliptic curve is easy to restore the private key when attacked by power analysis,which has become the weak point of the security of SM2 cryptographic algorithm.At the same time,the efficiency of elliptic curve operation directly affects the performance of SM2 cryptographic algorithm,which is also the key point of hardware implementation of SM2 cryptographic algorithm.Therefore,this thesis designs a lightweight SM2 cryptographic algorithm hardware circuit with anti power analysis attack ability for the security chip of Internet of things devices.The main features and innovations of this thesis are as follows:● The bottom-up design idea is adopted to complete the hardware design and functional simulation verification.In order to improve the security of the algorithm,this thesis proposes the negative modulus inverse operation of binary extended Euclidean algorithm.In order to reduce the consumption of hardware resources,an operation module compatible with modular inverse and negative modular inverse in prime domain is designed;● The coordinate axis randomization processing scheme is adopted to improve the point multiplication operation of Montgomery algorithm,and has the ability to prevent error injection attack.The power analysis attack test of the point multiplication operation of the improved Montgomery algorithm is carried out by combining prime time power analysis tool and MATLAB data analysis tool.The test results show that it has the ability to resist attack analysis attack.● TSMC 28nm process library is adopted to complete logic synthesis under the frequency requirement of 400MHz.The area report shows that the core operation logic area of SM2 cryptography algorithm is about 31000μm2,which meets the lightweight design specification requirements.Compared with the resource consumption reported in the same type of literature,the hardware circuit designed in this thesis reduces the hardware resource consumption by 70%,highlighting the lightweight characteristics of the circuit.