Design For Unified Architecture ECC And RSA Cryptographic Processor

In recent years, with the rapid development of Internet technology, informationsecurity has become an urgent problem. Public-key is an important method toimprove information security. Hardware cryptosystem has become a new researchfocus due to its many advantages. Based on the research on public-key cryptographyalgorithm for hardware, the paper proposed a cryptographic hardware coprocessor forprime field and binary field ECC and RSA. The design provided support forhigh-performance cryptographic arithmetic.Firstly, after analyzed of the flow of the RSA and ECC algorithm, the paperpresented that the modular multiplication is a communal computational bottleneckwhich restricts the computing speed of RSA and ECC. Solving the problem ofmodular multiplication is the most fundamental method to improve calculation speedof RSA and ECC. Then, in order to eliminate the division of modular operation whichaffect the computing speed, Montgomery algorithm is introduced as basic modularmultiplication algorithm. And, a variety of improved Montgomery modularmultiplication algorithms are introduced and analyzed. The CIOS algorithm is used asthe hardware implementation algorithm. In addition, in order to support both primefields and binary fields of ECC limited field, the dual field CIOS algorithm ispresented. Finally, the architecture of the cryptographic coprocessor design isproposed. Three modules, the computing, storage and controller unit, and theinterconnection between the three modules are designed. The dual-field multiplier inthe arithmetic unit is designed to support modular multiplication in both prime fieldsand binary fields.Final experimental results show that the optimized dual-field CIOS algorithm canachieve the required computation function. The hardware design could achievemodular exponentiation and modular multiplication function. Therefore, the proposedimproved algorithm and hardware architecture design is feasible. The design cancompute192bit,256bit,512bit,1024bit data bit wide of modular multiplication andmodular exponentiation. The required time to complete256bit prime field modularmultiplication,256bit binary field multiplication and1024bit modular multiplication were0.92,0.82and7.3microseconds at100MHz hardware clock. The synthesizedarea of all hardware modules is68K gates in SMIC0.18-micron CMOS technology.The Design has good speed and area ratio.