Research On The Hardware Implementation And Anti-attack Features For RSA Cryptographic Algorithm

Information security has become one of the important issues in the current sociallife, and cryptographic technology is the core technology of information protection.RSA algorithm, as one of the representatives of the public-key crypto system, has agood prospect in the field of cryptography. Based on the previous study on RSAmodular exponentiation algorithm and the Montgomery modular multiplicationalgorithm, this paper presents a special hardware implementation of RSA algorithm asa hardware accelerator which can against of side channel attacks. Comparing withusing general-purpose processor, ASIC and FPGA implementations for RSAalgorithm not only have an advantage in speed and area but also in security.Firstly, the algorithms of RSA encryption and decryption for hardwareimplementation are discussed and optimized in this paper. Montgomery PoweringLadder modular exponentiation and FIOS modular multiplication are adopted. Thedesign area is reduced significantly by reusing similar math operations. By usingspecial connection in the framework of RAM to avoid repeat moving of data inmodular exponentiation, the transmission time is reduced. Reconfigurable design inhardware implementation supports different lengths of secret keys in encryption anddecryption to satisfy the varying needs of customers. Secondly, consideringanti-attack method among the entire design makes the hardware design effectivelyprevent power attacks and fault attacks. In order to prevent power information leakagecaused by the last subtract step in modular multiplication, the design improvements ismade for the hardware implementation.The result shows that this design achieves high performance and high security.The data throughput of1024-bit RSA decryption is up to75Kbps at frequency of100MHZ and the logic area is only54K gates using SMIC0.13μm CMOStechnology.