Design And Research Of High-reliability BRAM Based On 28nm Standard CMOS Process

With the rapid development of artificial intelligence,People put higher demands on the performance of processors,FPGA as a semi-customized form of application-specific integrated circuit chips,because of its flexibility and high performance,it is widely used in military,aerospace and other fields.As a dedicated memory module in FPGAs,BRAM plays a key role in data processing and module interaction,and is an important functional unit in FPGAs.The BRAM module embedded in the FPGA not only needs to have the characteristics of large capacity,high performance,and high reliability,but also needs to have flexible scalability,support multiple working modes,and facilitate interaction with other modules in the FPGA.Therefore,this paper focuses on improving the reliability and performance of BRAM and increasing the scalability of BRAM,and designs a BRAM circuit with a capacity of 36 KB and optimizes it.1.The overall block diagram of BRAM circuit is introduced,and the working principle and timing of different read and write operations of BRAM circuit are analyzed theoretically.2.Design the memory unit circuit and conduct in-depth research and verification of its noise margin.The write interference problem faced by the memory cell was analyzed,and a circuit was implemented to avoid the write interference of the memory cell.3.Completed the circuit design of 36 K memory array and the peripheral control circuit design of BRAM.4.The layout design of BRAM was completed,and parasitic parameters were extracted for post-imitation verification.This paper uses the SMIC28 nm process to complete the design of a high-reliability BRAM circuit based on a fully customized design method,which can realize multiple read and write modes,multiple operating modes,multiple data bus widths,and ECC error correction functions to ensure the accuracy of read and write data.The simulation results show that the anti-interference structure proposed in this paper shortens the data writing time by 30.4% and the dynamic power consumption is reduced by 48.1% compared with the traditional structure,which improves the reliability of BRAM.Under different PVT conditions,BRAM can operate at up to800 MHz in standard operating mode.The quiescent power consumption in the TT process angle,voltage 0.9V,and temperature 27°C operating environment is 16.2μW,and the dynamic power consumption is 12.1μW/MHz,which meets the expected design goals.