Research On The NVM-based FPGA Block RAM Architecture

With the development of architectural intellectuality,there is a high demand for the processing power of the processor,especially for high performance processor chips and hardware acceleration,such as the CPU(Central Processing Unit),GPU(Graphic Processing Unit)and FPGA(Field Programmable Gate Array).In the field of embedded computing,FPGA has gradually become more and more popular computing platform.On the one hand,as the optimization theory of software algorithm become more and more mature,people focus on speeding up emerging applications using hardware.On the other hand,the reason is that the FPGA is more and more flexible programmability,the characteristic of parallel computing quickly was noticed by industry.FPGAs are more and more applied parallel computing and the application of highly efficient for industries.However,more and more complex scenarios of application for FPGA put forward higher requirements in the calculation,power consumption,storage capability.As FPGA chip integration is gradually improving technology level and on-chip SRAM storage capacity are also gradually increasing,the increasing of capacity and the requirements of application contradiction,which suggests "storage wall" problem,has restricted the development of FPGA in video processing and deep learning.With the development of non-volatile memory,low energy consumption and high integration characteristics are attracting academia and industry.Most noteworthy is that a new generation of STT-RAM(Spin transfer torque random access memory)is noticed by scholars and engineers.The characteristics of its high density and low energy consumption are considered the most promising to replace SRAM material.The capacity of SRAM-based FPGA block RAM(BRAM)is restrained by the low density and high leakage power of the current CMOS technology.In this work,we propose a non-volatile memory(NVM)based BRAM architecture which enables flexible conversions between single-level cell(SLC)and multi-level cell(MLC)states.We show that despite the high per-access latency and power consumption,NVM BRAMs in the MLC states reduce the routing cost between logic units and on-chip data storages,which potentially leads to a smaller over-all critical path delay and power consumption.Therefore,we propose NVM BRAM architecture and an EDA framework which adaptively packs data into SLC-state or MLC-state NVM BRAMs during FPGA design flow in order to achieve optimal critical path delay.Our study illustrates that a simple memory device replacement from SRAM to NVM leads to non-optimal system performance and power efficiency.On the other hand,compared with operating all NVM BRAM blocks in the SLC state width better per-access latency and power consumption,the proposed hybrid SLC-MLC architecture and design flow improves the critical path delay by 18.51%,with a system power reduction of 25.83%at the same time.Moreover,compared with the traditional "fast" SRAM-based BRAM blocks under the same BRAM area constraint,our hybrid NVM BRAM architecture improves the critical path delay by 8.55%on average,with an average system power reduction of 54.34%at the same time.