Integrated Circuit Test System STIL Vector File Parsing Module Design And Implementation

With the vigorous development of the integrated circuit industry,the chip design,chip manufacturing and chip packaging and testing technology related to integrated circuits have also continued to improve.Integrated circuit automatic test equipment can automatically and quickly measure circuit functions and electrical parameters and evaluate the measurement results to achieve chip testing.The vector compilation software is part of the equipment,according to the operating principle of the integrated circuit test equipment hardware system,the compiler is used to convert the data into the target machine code,output the object code into object files in various formats,and provide it to the test machine for execution.Vector compilation software uses pattern language to describe test tasks,of which STIL pattern language as a standard test interface language published by the IEEE Association,specifies in detail the symbols,syntax and rules used to describe the syntax,and realizes the universality of transferring digital test data from the generation environment to the test equipment,and the research of STIL pattern file compilation software is very necessary.The main research contents of this paper are as follows:(1)Analyze the requirements of vector compilation software from the perspectives of function and performance,including source file preprocessing function,parser function,compilation function,design data interface,g RPC communication interface,design test vector format and target file format,implement intermediate files and realize processing of up to 1024 channels and single channel maximum 128 M line test vector pattern file requirements.Design software solutions according to requirements,follow the basic principles of high cohesion and low coupling for software development,adopt modular design to improve cohesion,and use interface-oriented programming to reduce coupling,so as to improve development efficiency and reduce maintenance costs.(2)Using ANTLR4 parser to realize the parser,in order to control the parsing process to the greatest extent,the parsing scheme of grammar embedded actions is adopted,and the lexical analysis,syntax analysis and grammar tree generation in ANTLR4 are deeply studied and analyzed.(3)The preprocessing function adopts the method of scanning twice and analyzing in stages.That is,the preprocessor parser and the STIL parser are designed and implemented,the former will process the code comments,Include statements and macro definitions in the source file in turn,and input the processed file to the STIL parser,and then the STIL parser will identify and parse according to the definition order of the STIL language function block.(4)Serialize the parsed data structure object into a local intermediate file,and choose to use the deserialization mode according to the user command parameters to avoid repeated parsing of the same file,so as to realize the reusability of the pattern file and greatly improve the efficiency of integrated circuit testing.Through the above research and software testing,the main functions of the vector compilation software in this paper include: using the parser to accurately identify and parse the pattern language used in chip testing,and saving the data to the data structure or serializing it to a local file,which has achieved the design requirements and performance indicators.