Design Of A Low Power Low Ripple Step-Down DCDC Converter

With the continuous development of electronic technology,power management chips are widely used in various power supply fields such as portable electronic devices,and are an important part of various electronic devices.The power consumption and efficiency of power management chips have become important for current electronic products to obtain competitive advantages.one of the means.Compared with linear power supply,switching power supply has the advantages of small size and high integration,but its output voltage ripple is still an inevitable problem.Higher ripple will reduce the stability of the post-stage system.The research on low power consumption and low ripple of power supply is very meaningful.Based on the peak current mode control method,this dissertation designs a low-power and low-ripple step-down DCDC converter chip.The chip adopts dual-mode control mode,which works in pulse width modulation(PWM)mode under heavy load,and works in forced continuous(FCCM)mode under light load.At the same time,appropriate peripheral devices are selected to achieve low ripple in the full load range.sex.In addition,in order to reduce the power consumption of the chip,the chip adopts the idle-time shutdown technology to realize the shutdown of some unit modules under certain conditions,and a peak current sampling circuit with clock control is designed,which can realize intermittent operation,so as to The static power consumption of the chip is greatly reduced,and the circuit uses a switch tube to replace the traditional sampling resistor to sample the current,thereby further reducing the system power consumption.In addition,the gate drive of the power tube in the chip adopts a non-overlapping dead time control method to reduce the power loss of the driver stage,thereby further reducing the system power consumption.At the same time,the chip also integrates abnormal protection circuits such as over-temperature protection,over-current protection,under-voltage and over-voltage protection to ensure the normal operation of the chip and improve the stability and reliability of the chip.In this dissertation,the TSMC22 nm process is used,and the cadence virtuoso software is used to simulate and analyze the sub-module circuit and the overall system of the chip,and the layout design and post-imitation of the chip are carried out.The operating frequency of the chip is 2MHz,the input voltage range is 1.4V～2V,and the output voltage It is 0.6V,and the output voltage ripple is about 2mV,which can achieve low ripple output in the full load range.The total current of the internal sub-module is 19.74μA.When the load is 20 mA,the chip has the highest efficiency,about 91.02%,Compared with TI’s DCDC chip of the same type,the power consumption is reduced by about 30%.