Peak Current Mode Pwm Chip Research And Design

Along with the rapid development electronic information industry and the increasing demands of energy saving, modern switching power supplies found wider and wider applications and developed rapidly. The technology of switching power supply unified the advanced achievement of modern switching converter theory, integrated circuit and power semiconductor. It is featuring slight volume and weight as well as high efficiency and reliability and becoming the mainstream of modern power supply technology. With the rapid development technology of green energy,an ever-enhanced attention has been focused on the PWM rectifier in the field of power electronics. Integrated PWM switching power supplies have been widely used in communication systems, computers, etc. According to the dc-link energy storage elements; PWM rectifiers are classified into voltage-source PWM rectifiers and current-source PWM rectifiers. The current-source PWM rectifiers will be more attractive in medium power applications due to their advantages such as controlling the output current more directly and conveniently, and quicker dynamic response and interior short-circuit protection. Consequently, the research about peak current mode PWM controller chip has important significance.Based on the research on modern power supply technology, a peak current mode PWM controller chip with low standby power was designed. During the circuit research, the basic principle of monolithic current-mode and voltage-mode switching regulators are introduced at first. Then, the comparison between current-mode and voltage-mode is given in the thesis. With the comparison, we can understand the merits and drawbacks of these two topologies and then use them freely. This PWM controlling chip is integrated interior unique "green pattern" control circuit. The chip itself goes into cycle skipping at light loads, thus reducing the light loads power consumption. The efficiency is very high, especially under low load condition, because the output voltage is regulated by skipping clock cycles as necessary. The chip can disable the front-end PFC circuit during standby, thus reducing the no load power consumption. The author revised a new topology for this chip in terms of the customer's requirements and introduced five typical sub-blocks, such as inter_bias, soft_start and short-circuit protection, VCC_MGMT, FB_COM, PWM. And all circuits were given. The functional blocks were simulated in UMC 0.6μm BCD technology and verified by HSPICE. The results showed their performances met Spec well. This total circuit can generate high precise output regulation with input voltage 200V and 400V, and the output will remain in regulation with low output voltage ripple. The other features: 19.3V output voltage, 90W output power, 100kHz switching frequency, 2.8mA quiescent current at no load, 150mW standby power consumption.Based on the PWM principle analysis and circuit design in the beginning chapters, the author simulated whole chip circuit by applying EDA tools HSPICE .The typical performance characteristics include: load transient response, efficiency, output voltage ripple, quiescent current, output voltage temperature characteristics. The simulation results indicate that the PWM IC has achieved the expectation, both function target and electrical characteristics. Although there are disadvantages of this project, it is a worthwhile and valuable experience. Furthermore, the circuit principle analysis has been verified.