Research And Design Of DC-DC Converter Based On Peak Current Control Mode

With the blowout development of the electronics industry in recent years,power management chips are regarded as an extremely important voltage regulator module and are widely used in portable devices.It is moving towards high power density,high conversion efficiency,high transient response,digitization and other trends.The rise of wearable electronic products makes the performance requirements of power management chips more stringent and diversified,especially focusing on several important performance parameters such as low power consumption,high conversion efficiency,high transient response and low ripple.This article takes the Buck DC-DC converter as the research object,combined with a large amount of literature,focusing on low power consumption,high conversion efficiency,high transient response,wide operating frequency range,external clock synchronization,wide output voltage range,low ripple and other characteristics,designed a peak current control mode DC-DC converter.The input voltage range is required to be 1.6V-6.3V,the maximum output current is6A,the switching frequency is adjustable and it has an external clock synchronization function,the maximum conversion efficiency is greater than 95%,the maximum duty cycle is greater than95%,and the ripple output voltage is less than 3m V.This article first explains the research background and development trend of the DC-DC converter,and then makes a detailed analysis of the basic principles of the DC-DC converter's topology,working mode,modulation mode,and control mode.Subsequently,the system-level design of the chip is given,including system block diagram,electrical characteristics,functional description,typical application circuits,etc.,and the selection of peripheral devices and system power consumption are explained and analyzed.Then the working principle of each important sub-module of the system is introduced,and its circuit design ideas are explained in more detail.Among them,the unique design of the current sampling circuit greatly reduces the efficiency loss of the chip.The design of the internal working power supply and the improvement of the level shift circuit and BUFF circuit have produced considerable effects in reducing system power consumption and switching power consumption.The innovative soft-start module introduces a current-type neuron circuit,which can realize fast start,stable and reliable.Protection modules such as under-voltage protection,over-current protection,over-temperature protection,and bootstrap under-voltage protection ensure that the chip is protected from damage or abnormal operation caused by external factors such as power supply voltage,surge current,and ambient temperature.All the above functional modules are simulated and verified with the help of the Cadence platform and Hspice simulation software,and finally the overall layout of the chip is planned,the actual layout is given,and the layout verification and post-imitation are performed.The DC-DC solution proposed in this article is based on the CSMC0.18mm BCD process.Through the simulation results,the following conclusions can be drawn:When the power supply voltage V_in is in the range of 1.6V-6.3V,it has an output voltage range of 0.8V-0.95V_in.the conversion efficiency is as high as 98.6%,and the output voltage ripple is lower than 3m V.The working frequency range is 100KHz-1MHz,and it has an external clock synchronization function.When the output load current undergoes a 500m A jump,the output voltage overshoot is only 35m V,which has a high transient response capability.Through comparison with the work done by the predecessors,it is proved that the DC-DC scheme proposed in this paper has obvious advantages in terms of conversion efficiency,output voltage ripple,and output voltage range.