Design And Research On Power Factor Correction Circuit

With the wide application of switch mode power supply, the harmonics harmbecomes more and more serious. Therefore, this problem has been widely attractedattention in society. The Power factor correction technique is an effective means to restrainharmonic pollution in fundamentally. It has become a novel research aspect in electronicsfieldThe significance and development is briefly described in this thesis. And the concept,working mode and control mode are analyzed in detail. A boost active power factorcorrection circuit is designed. The circuit is working in the transition mode and peakcurrent mode. The starting current is only some ten μA, and the input capacitance is low,the working temperature is from-30℃to150℃. The main modules are analyzed anddesigned including under voltage lockout circuit, bandgap reference circuit, error amplifiercircuit, over voltage protect circuit, multiplier, over current detector circuit, currentcomparator zero current detector watchdog timer circuit, logic control and output circuit.Based on0.5μm5V/40V DPTM BCD process, function modules and the whole circuit aresimulated with spectre software. The simulation results show that the upper and lowerlimits for the chip starting voltage are12.2V and9V; the upper and lower limits for theover voltage protect current are42μA and10.1μA; the highest output voltage of multiplieris1.8V; the output voltage of the chip application circuit reaches a stable level about419V,the phase of the input voltage and the current are same, and the PFC can reach up to0.92.The layout is designed with candence software, The minimum size is2μm, theminimum size of npn emitter regin is80μm2, and the minimum size of pnp emitter regin is50μm2. The layout is succeed in design rule check and layout vs schematic.