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Design And Implementation Of Artificial Intelligence Processor Display And Auxiliary Storage Subsystem Based On FPGA

Posted on:2023-09-16Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y LiuFull Text:PDF
GTID:2558307061954189Subject:Computer technology
Abstract/Summary:
In recent years,more and more deep learning algorithms have been applied to realtime video stream analysis,which is of great value in intelligent monitoring,automatic driving and other scenarios.At present,field Programmable gate array(FPGA)is widely used in deep learning algorithm acceleration task,forming the artificial intelligence processor in the form of universal processor plus convolutional neural network acceleration module,expanding the solution of real-time intelligent video stream analysis on terminal devices.From a systematic point of view,in this thesis,a set of display and auxiliary storage subsystem is designed for real-time intelligent video stream analysis by artificial intelligence processor in the form of universal processor plus convolutional neural network acceleration module.In this thesis,the display subsystem of artificial intelligence processor based on FPGA is designed and implemented.Through the method of hardware and software cooperation,the real-time image is collected and the processed image is displayed.The artificial intelligence algorithm needs preprocessing such as image scaling,filtering and gray scale transformation.The realization method of hardware and software coordination is designed to improve the preprocessing speed.Compared with the traditional image input and output scheme based on Xilinx FPGA,the solution designed in this thesis simplifies the hardware design,the software control method is simpler,and cooperates with the AXI4 bus arbitration scheme to achieve system memory access optimization.In the design of auxiliary storage subsystem,different from AXI4 bus Round-Robin arbitration scheme in Xilinx ecosystem,this paper designs a dynamic priority access arbitration scheme.Compared with the arbitration scheme with fixed priority plus Round-Robin,this arbitration scheme can reduce the access latency of each device and improve the fairness and throughput rate of the system while ensuring the real-time image input and output.In addition,LVDS interface is also used in the output of video stream,and supporting the menu to adjust the brightness and contrast functions,making the system more functional and more integrated.Finally,the functional testing of the system,the quality and the acceleration ratio test of the image preprocessing algorithm,the latency,fairness and throughput test of the access arbitration scheme are carried out.The system designed in this thesis can correctly realize the input and output of real-time video stream,and the image preprocessing algorithm has a better speedup than the Intel i7-8700 processor running the same algorithm.The latency,fairness and throughput of the arbitration scheme are better than the traditional fixed-priority plus round-robin arbitration mechanism,which meets the design objective.
Keywords/Search Tags:Image processing, SoC, Bus, Arbitration, FPGA
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