Research On Secure And Lightweight PUF-based Key Generation Method

Traditional key generation and key storage schemes are under considerable threat as a result of the development of chip attack technologies.Physical Unclonable Function(PUF)eliminates this weakness of these schemes that are vulnerable to physical attacks and is often used in key generation applications.Key is the source of security for all upper-layer applications.At the same time,the applications such as embedded systems and Internet of Things(Io T)devices also put forward new requirements for lightweight key generation schemes.Therefore,this paper researches and implements a secure and lightweight PUF-based key generation scheme.Security is the most important feature for the key generation scheme,whereas most of the existing PUF-based key generation schemes lack comprehensive security analysis.Firstly,this paper analyzes the possible security loopholes in the existing PUF-based key generation schemes,and proves that the existing key generation schemes have entropy leakage under certain conditions.This paper quantifies the entropy leakage of key generation schemes in order to better investigate the applications of existing key generation techniques.Then this paper proposes a secure PUF-based key generation scheme to address the key leakage issue in existing schemes.Furthermore,the output response of the PUF is easily affected by environmental noise,which leads to wrong keys.This paper presents a bit error rate analysis method based on the proposed scheme to make sure that the generated key is reliable.Finally,a lightweight hardware implementation architecture based on hardware multiple and time division multiplex is proposed in order to meet the needs of application scenarios that are sensitive to hardware resource usage,such as embedded systems and Io T.This paper uses a large number of random experiments to prove the security of the proposed scheme and evaluates the key stability with an average bit error rate model.This paper implements the lightweight hardware architecture with FPGA and builds a test environment to verify the functions of the hardware module.Implementation results with FPGA show that the lightweight hardware architecture proposed in this paper does not require the use of additional RAM,and compared with existing key generation schemes,the use of Slice can be reduced by 37%.Compared with the state-of-the-art lightweight PUF-based key generation architecture,the ASIC synthesis results show that the hardware architecture proposed in this paper can reduce the area overhead by about 40%.