Research On High Speed Turbo Decoding Scheme For Indoor Wireless Image Transmission

In recent years,most emerging businesses and applications based on wireless image transmission technology have put forward higher requirements for the speed of the communication system and the safety and reliability in the transmission process.However,the digital signal is easily affected by the complex wireless network environment and channel conditions in the transmission process,resulting in the image jump and image discontinuity received by the receiver.Therefore,in order to ensure high-speed,efficient,low delay,safe and reliable information transmission under indoor conditions,the communication system introduces channel coding technology to avoid the occurrence of bit errors to the greatest extent.With excellent performance and flexible structure,Turbo code can meet the requirements of various communication systems for channel coding.However,due to the restriction of decoding algorithm and structure,the decoding rate of Turbo code is very low,which is difficult to meet the requirements of existing high-speed communication systems for throughput and delay.Therefore,this paper will improve the traditional Turbo decoding technology from the perspective of function and structure to achieve the design goal of 2Gbps decoding throughput.The specific research content for this goal covers the following aspects.Firstly,the research background and significance of Turbo codes are described in general.Then,combined with the research status of turbo decoding,the key problems of existing decoding technologies in the design process for high-speed,low delay and high reliability applications are summarized.To solve these problems,a specific decoding improvement scheme is given.Secondly,from the perspective of function improvement.Aiming at the serial processing method of processing bit by bit to obtain the metric information in the decoding process,the high radix algorithm is introduced to merge multiple bits,and the storage rules for updating the metric values of high radix are improved.The improved high radix decoding algorithm has improved in both speed and decoding performance;In addition,aiming at the shortcomings of fixed iteration times of Turbo decoding and failure of iterative update criterion when the decoding results are not convergent,an algorithm for automatically updating the iteration times under different SNR conditions is proposed,which effectively avoids the decoding delay caused by redundant iterations.Finally,from the perspective of structural improvement.In order to solve the problems of the traditional fixed parallel block decoding structure,such as excessive resource consumption,high computational complexity and single choice of parallelism in short frames,an arbitrary parallel block decoding structure is proposed.The proposed arbitrary parallel Turbo decoder allows flexible conversion between fully serial and fully parallel decoding structures,and is suitable for all interleaving lengths from 40 bits to 6144 bits.Combining the improved arbitrary parallel decoding structure with high radix decoding algorithm,an arbitrary parallel high radix high-speed Turbo decoding scheme is proposed,and the overall architecture design is given.For the key improved parts,such as parallel decoding processing module and high radix decoding module,the corresponding structure design and detailed processing process are given.Through the simulation of the improved high-speed decoding algorithm,it is proved that the high-speed Turbo decoding scheme proposed in this paper can achieve the decoding throughput of about 2.67 Gbps while ensuring reliable decoding,and achieve the design goal of 2Gbps.