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High Stability And Rapid Response LDO Research And Design

Posted on:2023-02-07Degree:MasterType:Thesis
Country:ChinaCandidate:X B HuangFull Text:PDF
GTID:2542307097993699Subject:Integrated circuit engineering
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As the potential of the integrated circuit industry is revealed,chip manufacturing has become an indispensable part of the daily manufacturing process.From national defense to small household appliances,the shadow of electronic chips can be seen.As the origin of all electronic products,the power quality and power management of the chip are related to the overall chip performance.With the further requirements of consumers for the service life and size of electronic equipment,the power supply also needs to achieve the highest balance between efficiency and cost through different power management chip structures and solutions.As the functions of electronic devices are becoming more and more abundant and diverse,it means that the power chip needs to increase the corresponding working modes to meet different functions,so as to reduce the power consumption and achieve the longest use time.Commonly used DC voltage sources are buck chopper voltage sources and low dropout linear regulators.Among them,low dropout linear voltage regulator(LDO)are widely used in power chips due to their advantages such as"clean" output voltage,low noise,stable circuit,low dropout voltage,fast transient response and low cost.This article uses SMIC 0.18μm CMOS process to design a low dropout linear regulator with transient response enhancement circuit.By using circuit simulation software to draw circuit schematic diagram and circuit layout,and then use the simulation software Spectre environment for simulation verification.The input voltage of the LDO in this article is 1.8 V-2.6 V,and the output voltage is 1.4 V.The output voltage of the bandgap reference source is 0.7 V,and the temperature coefficient of the output voltage is 29 ppm/℃.When the load current is 50mA and the load capacitance is 20 pF,the worst low-frequency(Power Supply Rejection)PSR of the LDO is about-68 dB.When the load capacitance is 20 pF and the load current is 50 mA,the phase margin is 92°,the average phase margin of the Monte Carlo simulation under the same conditions is 93°,and the phase margin of the circuit is still 49° when the load current is 10 μA.When the load current changes from 100 μA to 50 mA,the circuit can recover to 94%of the normal voltage within 1 μs,and when the load current changes from 50 mA to 100 μA,the circuit can recover to 95%of the normal voltage within 1 μs.
Keywords/Search Tags:LDO, transient response, PSR, high stability
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