| LDO(Low Drop-Out regulator-linear regulator),as the final branch of the power management system,can filter the input disturbance brought by the power supply terminal,and plays an irreplaceable role in the power management system.With the expansion of electronic circuits and the development of portable technology,higher requirements have been placed on the load capacity,endurance and output stability of LDOs.Therefore,transient enhancement technology and low power consumption technology have emerged as the times require.focus on.Aiming at two different application requirements,this paper designs a Capless LDO with low power consumption and high transient response(linear voltage regulator without off-chip capacitor)and a transient enhanced LDO with high stability.Aiming at the chip design requirements of small area and low power consumption for portable devices,this paper designs a capless LDO with low power consumption and high transient response.An Nmos power tube is used and combined with overshoot and undershoot suppression circuit structure to improve the transient response of the circuit.Since there is no off-chip capacitor,the stability design of this type of circuit is a difficult point.In this paper,an improved Class-AB OTA(operational transconductance amplifier)is used as an error amplifier to eliminate the low frequency pole,and a super source follower is used.The frequency compensation of the system and the Miller capacitance are provided to realize the stability of the system.Finally,the system can provide a stable voltage with a load current switching time of 1ns.LDOs with off-chip capacitors use off-chip discrete devices for frequency compensation.The accuracy of discrete devices is lower than that of integrated devices,and at the same time,it is susceptible to external environmental interference,resulting in inaccurate compensation.In order to further meet the high stability requirements of industrial-grade LDOs,a highstability transient enhanced LDO with on-chip compensation is designed in this paper.In view of the pole coincidence problem caused by the load change,this paper uses a folded cascode op amp as the error amplifier to ensure the loop gain,and at the same time cooperates with a lowresistance output buffer to push the gate pole of the power tube to high frequency,so as to reduce the system The stability analysis is transformed into the well-known classical two-stage op amp stability analysis,and then the Miller capacitor is used for frequency compensation to realize the stability of the on-chip compensation of the system.While pushing the gate pole away,the buffer increases the system bandwidth from hundreds of Hz to several Mhz,which can realize ns～μs level load current switching,and the system has strong transient characteristics.The two structures designed in this paper use TSMC 180 nm CMOS process to complete the chip simulation and layout design.The layout area of the Capless LDO circuit is184μm×222μm.The chip is suitable for 2.5-3.6V input and 1.2V output.The post-simulation results show that the LDO quiescent current is only 0.57μA.Under the switching time of 1ns,the transient voltage is less than 260 m V,and the recovery The time is less than 450 ns.Under the worst PVT condition,the minimum phase margin is greater than 45°,the linear adjustment rate is less than 1.37 m V/V,and the maximum offset is less than 2.1m V when the load current changes,which meets the power supply requirements for the subsequent circuit.For high stability transient enhanced LDO,the circuit layout area is 354μm × 130μm,the chip is suitable for 2.5-5V input,1.8V output.The post-simulation results show that the transient peak value is less than 30 m V when the load is switched from 0-100 m A.Under the worst PVT condition,the minimum PM>57.5°,the linear adjustment rate is less than 0.723 m V/V,and the maximum offset is less than 20 m V when the load current changes,which meets the application requirements of industrial-grade LDOs. |
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