The Design And Verification Of SpaceWire Node IP Core

With the development and advancement of technology,the pace of human exploring space is becoming more and more frequently.Meanwhile,spacecrafts carry more and more equipments and facilities,especially the imaging type instruments,which leads to the amount of data increasing rapidly.The traditional low-speed bus has not adapted to the rapid development of space technology.SpaceWire is a high-speed,serial,full-duplex bus,with its good performance in mistake searching,abnormity managing and fault renewing.SpaceWire can greatly meet the demand of on-board data transfer nowadays.Based on deep understanding of SpaceWire bus protocol,this paper designs the IP core in Verilog HDL and also develops the PCI simulation test platform.The use of programmable logic device for IP core designing has advantages of low cost,high reusability and portability,which can be easily applied in SOC systems.The system hardware platform combines SpaceWire bus and PCI bus,which makes the IP core testing and verification more flexible and convenient.The results of conformance testing based on standard instruments show that the design of IP core meets SpaceWire protocol.At the same time,the point-to-point communications verification is tested through hardware platform,and the test result accords with the design requirements.