Design And Validation Of SpaceWire Routing IP Core

With the development of space exploration technology, satellites carry more and more payloads. Mass data communications and processings require the internal communication system should be with high-speed, agility, abnormity managing, fault protection and fault renewing. The on-board data bus, which connects payloads together, plays a very important role in the whole system. The reliability, speed and flexibility of the on-board data bus network have direct effect on the performance of the whole on-board electronic systems.SpaceWire proposed by ESA in 2003 is a full-duplex, bidirectional, serial, point-to-point data bus standard. It greatly meets the demand of high-speed on-board data transfer nowadays. Recently, SpaceWire technoloty has been paid great attention. Many agencies have done researches on it, such as ESA, NASA, and JAXA. They have also applied SpaceWire technology to their space missions successfully.In this project, the design and validation of SpaceWire routing IP core has been realized on the base of SpaceWire Codec IP core. The design is implemented by Verilog programming, while the validation is done by simulations in ModelSim and the hardware validation. The hardware validation contains the design of SpaceWire PCI card and the related software user interface. The user interface can configure the SpaceWire routing module, exchange data, configure the SpaceWire link and track the link status through the PCI bus. Through lots of simulations and validations, the system proves to work very well.