Research On Highly Reliable SpaceWire Routing Mechanism Based On Field Programmable Gate Array

The SpaceWire bus is a bus standard which is specially designed for high-speed data transmission by the European Space Agency Based on two commercial standards IEEE 1355-1995 and IEEE 1596.3.SpaceWire routers are an important part of the SpaceWire network that enables high-speed,large amounts of data exchange between the host and the peripherals.However,using field programmable gate array to achieve the router for the space environment,highly vulnerable to space radiation and the occurrence of single event upset,so this paper studies the high reliable SpaceWire routing mechanism based on FPGA,and has carried on the simulation and board level verification..The main contents of this paper are as follows:(1)Analyzes the advantages and disadvantages of common bus of aeronautics and astronautics,especially SpaceWire router at home and abroad research progress and the realization of the SpaceWire router and fault-tolerant technology present situation and existing problems,gives the solution in this paper.At the same time,the six sub-protocols of SpaceWire bus are studied to provide theoretical basis for the design of high-reliability SpaceWire router.(2)Based on the analysis of the typical SpaceWire router structure,the overall scheme of the System-on-a-Programmable-Chip system structure adopted by the highly reliable SpaceWire router is given,and the corresponding fault-tolerant method and self-healing program are designed.This paper presents the software,hardware platform and programming language,and analyzes the principle and realization method of the bitstream relocating technique.(3)A single mode SpaceWire router based on System-on-a-Programmable-Chip is designed.The test system is written and verified,and the board level verification is realized on the FPGA development board.Designing the test and verification system of SpaceWire router repair mechanism based on bit stream relocation,and giving the detailed design process,especially the dynamic partial reconfiguration design and bit stream repositioning design method;The verification system is implemented on the FPGA development board,which verifies the feasibility of partial reconfiguration by bit stream relocation technology,and analyzes the influence of bitstream relocation technology on bit stream storage space and the time needed.(4)Aiming at the problem that the repaired state of the faulty module is out of synchronization with other modules,a state recovery and synchronization technology based on system work input and real-time self-healing Triple Modular Redundancy system is proposed,and hexadecimal circular adder,SpaceWire node state machine and Receiver FIFO as examples,the technology has been verified by simulation.A TMR-structured SpaceWire router test system with state synchronization is designed and tested on the ML507 development board.The SpaceWire router node codec with TMR structure and self-healing and status synchronization function is designed.The test system is built on the ML507 development board.The results show that the system not only can recover the failed module,but also can guarantee the repair status of the failed module Synchronize with the other two health modules,and the whole process does not interrupt the system function.