Design And Implementation Of The Embedded Master Corprocessor In Airborne Data Acquisition System Based On EtherCAT

With the rapid development of large aircrafts,the requirement of manifold,abundant and real-time in airborne data acquisition is increasing,while the traditional PCM system,with the problem of clumsy framing,low speed transporting and high costs operating,can not meet it any longer.EtherCAT is a real-time Ethernet technology which through using bus topology at the physical layer as well as a forward immediately after receiving communication method rather than the traditional storage and forward way,has overcome the real-time and delay jitter shortage of Ethernet using in real-time control system,and is able to meet the airborne test system for real-time,high-speed,synchronous,and reliability requirements,with good prospects for development.Based on the research project of the laboratory named "Design and implementation of airborne data acquisition system based on real-time Ethernet",this thesis mainly focuses on the FPGA design of the master coprocessor.Firstly,the status and the network trend of airborne test are described briefly and the advantage and the necessity of EtherCAT introduction is analyzed.In the second part,after illustrating the EtherCAT protocol,the hardware design of the system is discussed in detail,including the design of functional block diagram and circuits.Finally,the FPGA implementation of the master coprocessor is developed.The simulation with Modelsim and the verification on the PCB show that all of the desired research targets is achieved.