Research On Whole Chip ESD Protection Based On LVDS Interface Circuit

Currently in the cusp of the information age,the speed and efficiency of data transmission is getting faster and faster.Interface circuit plays a very important role as the bridge between the core circuit and the external device.A variety of interface circuits have been developed.Low-voltage differential signal(LVDS)interfaces are widely used in display,image and radar fields for their low power consumption,strong antiinterference ability,good compatibility and higher transmission rate.However,the performance and efficiency of the chip are often interfered by electrostatic discharge(ESD)events in the normal operation of the chip,and even damage the entire circuit.Therefore,ESD protection is very necessary for this interface circuit.In this thesis,the driver and receiver of LVDS interface circuit are protected by full-chip ESD in 0.35μm BCD process.First,the knowledge of ESD full-chip protection and two test models are introduced.The transient pulse waveform is used to simulate ESD events to get the I-V curve of the device.Then it introduces the basic principle of the whole chip protection and the basic architecture of the whole chip protection network,including the whole chip protection network based on pad-clamp circuit and public ESD discharge bus.Analysis of the specific LVDS receiver and driver of each I/O circuit,the two types of internal circuit to protect the main part can be divided into input port,output port and enable port,focusing on the analysis of the two types of interface chip these three ports of the window.Various single devices used for I/O port protection are studied.According to the requirements of HBM between window and port,we choose SCR devices for protection and optimize them,so that the trigger voltage can be significantly reduced and the maintenance voltage can be improved.The RC_CMOS architecture is selected for the protection between power and ground,and uses its special RC-coupled delay characteristic to turn on and off ESD current drain devices.Finally,a suitable full-chip protection scheme is developed and the upper chip is mounted with appropriate devices.This protection uses the full-chip protection network of Global ESD discharge bus.The characteristic of this protection network is that it only needs to mount an ESD protection device capable of two-way protection on the protected port,and then the ESD current discharge can combine the discharge current through this device or other devices,and the discharge between any pins can pass through two devices at most.The parasitic effect caused by this is reduced.For example,in PS/NS mode,ESD protection devices are directly used to discharge the current,and in PD/ND mode,the current is discharged through a combination path.Analysis of the results after the flow plate,through the test for LVDS receiver input port protection can basically reach HBM 15KV,output port and enable port can reach HBM 4KV;LVDS receiver input port and enable port can basically reach HBM 4KV,output port can reach HBM 15KV.