On-chip ESD Protection Device Principle、Structure And Performance Research

With the development of integrated circuit industry and the progress of process technology,the chip size is shrinking day by day,and the application environment of the chip is becoming more and more complex.IC designers have higher requirements on the reliability of chips,and electrostatic discharge(ESD)design has become an increasingly important part of IC design.Gate grounded n-metal oxide semiconductor(GGNMOS),silicon controlled rectifier(SCR),embedded metal oxide semiconductor structure SCR and bi-directional SCR(DDSCR)are the effective protection device commonly used in ESD protection.On-chip integration of ESD protection devices is an important development direction of ESD protection design,and the key is to design high robustness ESD protection devices.This thesis is based on three key issues of ESD design:(1)How to improve the current discharge capacity of devices per unit area;(2)how to improve the uniformity of conduction of devices;(3)how to resolve the contradiction between holding voltage and failure current.According to the optimized design of low voltage unidirectional ESD devices and high voltage unidirectional and bidirectional ESD devices,the main work and innovations are as follows.1.According to the physical mechanism and theory of the device,the breakdown voltage of the device is optimized based on the avalanche breakdown characteristics of PN junction,considering the ionization rate of the breakdown surface,the electric field and the doping concentration at both ends of the junction.The emission efficiency of the bipolar transistor depends on the injection density and the emitter width.Base transmission coefficient is considered based on base width,base minority carrier diffusion coefficient and base minority carrier life.Emitter injection efficiency and base transfer coefficient affect the amplification coefficient of parasitic PNP and parasitic NPN,and then affect the ESD robustness of SCR structure.On the basis of summarizing the principle of ESD devices,a new ESD protection device is designed by combining theoretical analysis with TCAD simulation and verified by producing and testing.2.In the application of unidirectional high voltage ESD,holding voltage and failure current are always the key factors to be considered.(1)In this structure,the SCR is segmented to improve the emitter injection efficiency of parasitic SCR,thereby increasing the holding voltage.Through the 3D simulation of TCAD,its working mechanism is verified.Based on 0.5μm standard CMOS/DMOS process,TLP test results show that the holding voltage(7.4 V)of the segmented SCR is 300%higher than that of traditional SCR(2.35 V),and the FOM is increased from 4.8 to 24.7 and can reach 5 times.(2)In order to optimize the failure current of LDMOS-SCR,the deep current path of SCR will restrain the current discharge in NMOS channel.In this structure,the NMOS channel suppressed by SCR can discharge current through the voltage drop caused by parasitic gate capacitance to well resistance,and there are two current discharge paths:SCR path and NMOS channel.Based on 0.18μm Logie-E 6/18 V process,TLP test results show that the 4-finger LDMOS-SCR device with a layout area of 119×79μm~2 can effectively increase the failure current by 30%(from 6.62 A to 8.6 A)and increase the ESD stress tolerance of LDMOS-SCR from 10000 V without affecting the design window.3.In high-voltage Dual-directional applications,it is more important to maintain the relationship between holding voltage and failure current.(1)In view of the contradiction between the failure current and the holding voltage of DDSCR,a device structure with embedded gate and variable gate voltage is proposed,which can improve the holding voltage by influencing the voltage drop formed by the built-in electric field of drift electrons at the holding point.By means of TCAD simulation,the doping concentration of the channel under the gate can be adjusted by the variable voltage on the gate.Based on0.5μm standard CMOS/DMOS process,single finger APGDDSCR can increase the holding voltage by 40%(from 13.37 V to 18.781 V)without reducing the failure capability.Under the condition of holding voltage higher than 13.2 V,the core circuit can withstand ESD stress of 15000 V at 30 V and ESD stress of 22000 V at 40 V.(2)In view of the optimization of failure current discharge capability of DDSCR,a device with double PNP structure is proposed by using DDSCR device structure.By increasing the emitter resistance of SCR2,SCR2 can work after SCR1 is turned on.The working mechanism of this device is analyzed by TCAD simulation.The device is embedded with additional p+,and two groups of SCR current discharge paths can be formed.Based on 0.5μm standard CMOS/DMOS process,the embedded structure has no effect on the working window,and it can improve the failure current without reducing the holding voltage.Under the 40 V design window,it can withstand ESD stress of 45000 V.