Design Of Analog Baseband And ADC For 24 GHz Millimeter-wave Radar

With the popularity of automobiles,people's demand for safety performance during driving is increasing and vehicle-mounted radars are widely used.Millimeter-wave radars in the 24 GHz band are widely used in short-range detection of vehicle-mounted radars due to their low cost,ease of integration,and ease of implementation.Based on the 55 nm CMOS process,this paper designs an intermediate frequency(IF)signal processing chip for the modified 24 GHz dual-mode millimeter-wave radar transceiver,including a low-noise analog baseband(ABB)and a low-power Sigma-Delta modulator(DSM).The main research work and achievements are as follows:(1)The mathematical principle of detectng speed and distance in FMCW mode and Doppler mode is analyzed.The test results of the IF signal processing circuit of the first version of the radar chip are listed,and the system structure and the link buget of the modified 24 GHz radar are proposed.Combined with the indicators of the receiving front-end and the transmitting front-end and the path loss of the millimeter wave in the transmission process,the performance indicators of the analog baseband and analog-to-digital converter in the modified radar system are calculated.(2)A low-noise analog baseband circuit is designed,including low-pass filter and DC offset cancellation(DCOC)loop.In order to facilitate the independent adjustment of gain and bandwidth,a low-pass filter is formed by two-stage Tow-Thomas biquads,in which the resistors are programmable array structures so that the filter can be used as variable gain amplifiers at the same time.A current injection type DC offset cancellation scheme is proposed,which can calibrate the DC offset deviation without losing the energy of the 10 Hz?555 k Hz extremely low frequency IF signal,and avoid using a large area of capacitors in the chip.In order to obtain low-noise performance at very low IF signal frequency,on the one hand,the input pair transistors of the operational amplifier and the current source transistors of the DCOC use NPN transistors with less low-frequency flicker noise,and on the other hand,the first-stage operational amplifier adopts a chopping modulation technology.The technology realizes the separation of the signal and the input noise in the frequency domain through the function of the two-stage choppers,and the noise at the low frequency is pushed to the high frequency.The core layout area of single path is956 ?m×292 ?m.The post-simulation results show that: under the condition of 2.5 V power supply voltage and 40? TT process corner,the transient gain range covers0?70 d B,and the-3d B bandwidth is more than 600 k Hz;the noise figure in FMCW mode and Doppler mode are both less than 30 d B;when there is 200 m V DC offset at the input end,the output residual DC offset is only 5 m V;the phase margin of three differential mode loops and one common mode loop is sufficient,and the single-channel analog baseband power consumption is 14 m W.(3)Since no digital filter is involved in this paper,a low power Sigma-Delta modulator is designed.The modulator adopts a single-loop fourth-order feedforward structure.In order to save power consumption,the integrator is a continuous-time type.The feed-forward structure reduces the performance requirements of the post-stage operational amplifier and saves power consumption significantly;accordingly,the summation circuit adopts a resistive passive structure.At the same time,since the single-bit quantizer output is only low level or high level,it is directly implemented by a comparator,which saves power consumption and avoids the deterioration of the system performance caused by the mismatch of the multi-bit feedback DAC unit.The core layout area of single path is 343 ?m×253 ?m.The post-simulation results show that:when the sampling frequency is 40 MHz and the input signal frequency conforms to the coherent sampling relationship,the Sigma-Delta modulator can obtain an effective number of bits of 11.3 bits,a signal-to-noise distortion ratio of 69.8 d B and a spurious-free dynamic range of 75.9d B within the 600 k Hz bandwidth under the condition of 40? TT process corner;and the signal-to-noise distortion ratio obtained at 5 process corners and three temperatures of 40?,-40? and 120? is greater than 55 d B,power consumption is less than 1.5m W.(4)The cascading simulation of the analog baseband and Sigma-Delta modulator in the modified 24 GHz radar chip designed in this paper is carried out,and the cascading overall can obtain an effective number of bits of 9.8 bits and a signal-to-noise distortion ratio of 61 d B.A plan for independent testing of the two modules is also given at the end.