Design Of High Linearity Driver Amplifier Based On GaAs Process

The driver amplifier is often used as a predriver of a power amplifier,but can also be used directly as a final stage power output at lower power conditions.Its location dictates certain requirements for its linearity.In addition,the booming development of5 G technology in recent years and the changing modulation means of communication have also placed increasing demands on the linearity of driver amplifiers.Gain is another important metric for drive amplifiers,and Darlington structures can provide high and flat gain in single-stage amplified circuits,suitable for use in wider bandwidth amplification circuit designs.GaAs HBT devices are common in the design of power amplifiers.With higher breakdown voltages and ultra-high electron mobility compared to conventional Si substrates,GaAs offers more diverse possibilities for high power applications,while HBTs offer high electron injection efficiency and easy access to high current gain,so GaAs HBT devices are chosen to design drive amplifiers.The main innovations in this thesis are the bias circuit and the use of a new linearity enhancement structure.The combination of self-adaptive biasing and active biasing allows for both linearity and stable input impedance,reducing the temperature sensitivity of the circuit.The linearity boost structure provides a drain loop for non-linear third-order harmonic currents by introducing a post-distortion transistor,which has a significant suppression effect on third-order-intermodulation effect,improving the linearity of the circuit while also having the usefulness of control the high output impedance of Darlington structure.The circuit was simulated using ADS software,fabricated using a 0.2?m GaAs HBT process.After taped out and tested,the conclusion confirm that the new circuit structure was effective and feasible.The final set of measured results show that the gain exceeds 20 d B in the 0-2GHz range,the input return loss is less than-10 d B,the output return loss is less than-15 d B,the 1d B compression point of the output power is greater than 19.5d Bm,and the third-order intercept point is up to 35 d Bm at 500 MHz,with an overall chip area of 0.6mm*0.65 mm.