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Design Of Data Processing Module In DBI Acquisition System

Posted on:2022-11-15Degree:MasterType:Thesis
Country:ChinaCandidate:T ZhangFull Text:PDF
GTID:2518306764975389Subject:Automation Technology
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With the rapid development of electronic information technology,data acquisition system plays a vital role in electronic information engineering,and has been widely used in many fields such as testing,communication,and military industry.At present,the transient characteristics and complexity of signal are becoming more and more rise,which puts forward higher requirements for the bandwidth and sampling rate of the acquisition system.However,the existing analog-to-digital convert chip can no longer meet the development needs of single-channel acquisition system bandwidth and sampling rate.The data acquisition system based on parallel sampling architecture has gradually become a research hotspot.In order to improve the system bandwidth and sampling rate,an ultrawideband high-speed data acquisition system based on Digital Bandwidth Interleaved(DBI)sampling technology and Time Interleaved sampling technology is implemented in this thesis.Error of frequency overlapping band and the phase-frequency response distortion error of all passbands in the acquisition system are mainly studied,and the hardware implementation structure of error correction is designed respectively.The main research contents of this thesis mainly include: 1.The mathematical model of Digital Bandwidth Interleaved technology is studied and analyzed,and the perfect reconstruction condition of the input signal is deduced.Based on the technology,a Digital Bandwidth Interleaved acquisition system with four sub-bands was successfully built,and the data processing modules in the system were introduced.In order to meet the needs of data acquisition and processing,the system clock synchronization scheme of the system is introduced in detail,and the characteristics of two different data streams in the system are analyzed.2.The error of frequency overlapping band in the Digital Bandwidth Interleaved acquisition system is researched and analyzed.Combined with the mathematical model of the error,the influence of the error on the system is studied,the frequency boundary of the overlapping band is calculated.According to the characteristics of the overlapping band error,correction modules for nonlinear phase and linear phase error are designed,including the design of fractional delay filter,synchronous calculation of integer delay values for four subbands and the design of all-pass compensation filter 3.The phase-frequency response distortion error of the all-pass band is studied and analyzed,and a measurement method of the phase-frequency response distortion error of the system all-pass band is introduced.Combined with the nonlinear characteristics of the error,a phase error compensation module based on second-order node cascade is designed,and the design method of all-pass compensating filter parameters is introduced.4.According to the characteristics of two different data streams in the system,an interrupt status register mechanism is designed,which is respectively applied to the hardware implementation structures of fractional delay filter,integer delay and secondorder section cascaded all-pass filter.the resources consumption of these structures and coefficient quantization error of the filter are analyzed.Through the research on the above content,a Digital Bandwidth Interleaved acquisition system with a bandwidth of 20 GHz and a sampling rate of 80 GSa/s has been successfully implemented.Finally,the sampling rate,bandwidth and other indicators of the system are tested and verified.The correctness of the correction module is verified by comparing the effects before and after the correction of the phase-frequency response of the overlapped band and the all-pass band,and then the perfect reconstruction of the input signal is achieved.
Keywords/Search Tags:Digital Bandwidth Interleaved, error of frequency overlapping band, all-pass band phase-frequency response distortion, error correction, interrupt status register
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