Design Of Analog PHY Of USB PD 3.0 Protocol Chip

With the development of the integrated circuit industry,the performance of mobile electronic devices is rising,but the endurance of the devices is difficult to improve effectively.To solve this problem,fast charging technology was invented.As one of the current mainstream fast charging technologies,USB PD 3.0 fast charging protocol has high charging power and many charging gears and good universality.As a common protocol standard,its generality and universality are better than other private protocols,and it has better research value.This thesis designs the analog physical layer of the USB PD 3.0 fast charging protocol chip for Sink.A transmitter consisting of an edge-generation circuit and a class AB output circuit is designed for the protocol’s specified index.Due to the parasitic parameters and environmental factors,the received signal has voltage drift.To address this problem,this thesis designs a receiver consisting of a preprocessing circuit and a differential hysteresis comparison circuit to receive the signal correctly and ensure the signal integrity.For the protocol index and other circuit requirements,a power management circuit consisting of a bandgap reference circuit,a voltage-to-current circuit,and an LDO regulator is designed to provide the voltages and currents.For the needs of edge-generation circuit in the transmitter and digital circuit in the chip,a voltage-mode RC relaxation oscillator is designed by using the first-order temperature compensation method,and the structure is improved to reduce the area,while the circuit can provide a more stable clock frequency by trimming.And the VBUS detection circuit is designed to detect the VBUS voltage to control whether the chip is enabled or not,and the power-on detection circuit with hysteresis structure is designed to detect whether the bandgap reference circuit is powered on successfully,and the CC-connection detection circuit is designed to detect the connection of the Type-C interface and the charging power in non-PD mode.In this thesis,the circuit is designed in 0.18μm BCD process,and the simulation shows that the high voltage of the transmit signal is 1.1142V～1.1366V,low voltage is 0.0074V～0.0456V,the voltage swing is 1.0905V～1.1129V,the rise time is 314.87ns～492.98ns,the fall time is 417.69ns～505.28ns,the output impedance is 38.80Ω～69.95Ω,and the results meet the requirements of USB PD 3.0 protocol.While for signals with the low voltage range of0.3325V～0.2325V and high voltage range of 0.6425V～1.5325V,the receiver can successfully receive signals.The receiver is capable of receiving signals with good resistance to voltage drift.