Research On Polar Code Decoding Algorithm Based On Fast-SSC

Polar code is a family of error correction channel coding scheme that can be strictly proved to achieve Shannon limit in binary discrete memoryless channels.It has attraceted wide attention from experts and become one of the 5th-Generation communication standards.Due to the encoding structure,the decoding algorithm has natural serial characteristics,such as the successive cancellation(SC)decoding needs to traverse a full binary tree constructed by the location information.In order to improve the parallelism of decoding algorithm,this paper studies the throughput and decoding delay of polar code decoding algorithm,then designs a decoder architecture.The main work as follows.1)Analying the path law of different leaf nodes in the List-Fast-SSC decoding algorithm,we propose a simplified sorting architecture.The architecture first constructs M*L ordered candidate path matrix by pre-sorted network.Then,using the proposed lossless pruning algorithm to prune the candidate paths that are not in the L most reliable path obviously.Finally,we propose a compatible sorting network that combines the advantages of GBS and OES.The data shows that for L=32,M=8,the proposed architecture can remove 66.7%paths and save 52.3%CASUs and 25%stages than OES network.2)Based on List-Fast-SSC decoding,this paper designs a parallel List-Fast-SSC decoding algorithm,which splits the original binary tree into two that are recorded as left and right trees,and the two trees can be decoded in parallel.The number of nodes in one decoding tree after parallel decreased 40%.We design the leaf node decoding method generated by parallelization decoding tree.The most important is designing the appropriate extended path method in the two aspects that complexity and decoding delay of sorting network.Simulation shows that,when L=32,BER=10-5,the proposed algorithm is 0.1dB better than List-Fast-SSC decoding algorithm.3)This paper designs the hardware architecture of parallel Fast-SSC decoding algorithm,analyzes the impact of different quantization schemes on decoding performance and resource consumption,then designs storage scheme and control scheme for the characteristics of deep pipeline.Finally,we design a parallel pipeline decoding architecture based on two pipelines,which has high throughput and low decoding delay.A decoder utilizing the proposed architecture was implemented for(1024,512)polar code on FPGA platform that Altera Stratix V 5SGXEA7N2F45C2 and the software using Quartus ? 15.0.Simulation shows that at 285MHz,the throughput rate can reach 291.84Gbps.