Design And Realization Of High Resolution Delay Synchronization Control Module

Signal delay technology is used in time measurement,space measurement,and satellite-to-ground timing.With the development of delay technology,the requirements for the resolution,delay range and repetition frequency of signal delay are getting higher and higher.In Thesis,the delay method of high-speed high-resolution acquisition and reconstruction is studied,and a high-resolution delay synchronization control module is designed and implemented.The main research contents are as follows:1.The principle and method of related time delay technology are studied.Aiming at the problem of signal and system synchronization,two methods based on TDC and TAC to measure time fraction and then compensate are discussed,and their shortcomings in phase measurement error and real-time performance are analyzed.By modeling and analyzing the relationship between signal phase jitter and high-speed sampling rate and resolution,a delay method based on high-speed and high-resolution acquisition and reconstruction is proposed.A 12-bit ADC with 1 GSPS is selected to sample the signal,and a DAC with the same sampling rate and resolution is used to reconstruct the signal,ensuring low jitter of the reconstructed signal.2.Completed the design of high-speed and high-resolution acquisition and reconstruction circuit.According to the requirements of signal integrity,high-speed and high-resolution ADC and DAC need to provide low-jitter clocks and stable power supplies.The influence of clock jitter on the system is analyzed,a dual phase-locked loop structure is used to generate a low-noise clock,the loop filter circuit is designed,and the clock simulation tool is used to simulate.According to the voltage and current requirements of the complex system,the design of the power supply circuit is completed.3.Design and complete the digital logic system.For the high-speed LVDS data stream generated by ADC sampling and the data required for the high-speed DAC to reconstruct the signal,IDDR is used in the FPGA to receive data,and ODDR to transmit data.Multiple digitized waveforms are stored in the FPGA,and the delay time is counted before the waveform is sent to the DAC,thereby achieving a wide range of delays and a high repetition rate.For the problem of high sampling rate and large amount of data stored per unit time,a method is proposed to reduce the difficulty of storage by intercepting waveform segments,so that the system can achieve a delay of 1 ms when the repetition frequency of the input signal is 10 k Hz.The problem of real-time delay is solved by storing the sampled waveform data corresponding to the time information and storing them together.4.A high-resolution digital delay device is used to achieve a delay with a resolution of 10 ps.The nonlinear problem is discussed,the delay curve is measured,and the inverse function method is used to correct it.The time delay interpolation method is adopted to realize the combination of high resolution and wide range of delay.Finally,after testing,the designed high-resolution delay synchronization control module has an adjustable delay range between 1us and 1ms,the delay resolution is better than 10 ps,and the trigger repetition rate is greater than 10 k Hz,which satisfies the system's precise delay and synchronization requirements.