Research On High-order BOC Modulation Signal Acquisition For Satellite Navigation System And Verification On FPGA

Nowadays,satellite navigation system has been widely used in our daily life.It has become an indispensable and important application.To provide better services,the research on acquisition and tracking of navigation satellite signals is of great significance.As a key part of baseband signal processing in navigation receivers,the acquisition of satellite signals has a deep impact on the performance of navigation receivers.Binary offset carrier modulation is becoming more and more common in the signal modulation mode of the new generation navigation satellite system.Compared with the traditional modulation mode,it has higher acquisition accuracy and stronger anti-multipath quality.However,the multi-peak effect of its autocorrelation function also brings difficulties to the design of acquisition algorithm.This thesis mainly studies the acquisition of high-order BOC signals in navigation satellite system and the verification on FPGA.Firstly,this thesis introduces the principle of satellite navigation.As the theoretical basis of acquisition algorithm research,it introduces the signal sequence characteristics of Beidou satellite navigation system signal generation mode and the generation of BOC modulation signal including the related properties of BOC signal.Secondly,it analyzes that the essence of signal acquisition is a three-dimensional search process of satellite number,Doppler frequency shift and chip delay.Three classical acquisition algorithms are used for acquisition of BOC(15,2.5)signal.Then,three acquisition algorithms,ASPeCT,correlation function reconstruction,cosine subcarrier cancellation based on BPSK-like,are mentioned and their simulation is carried out.According to the characteristics of high-order BOC signals,this thesis designs Time Parallel Acquisition with Subcarrier-Cancellation Peak Detection(TPA-SC)algorithm,and optimizes the overall complexity of the algorithm by combining the resampling method.In 40 dB·Hz carrier-to-noise ratio environment,the algorithm can ensure that the acquisition probability is above 0.9 when the false alarm probability is less than 0.001.The TPA-SC has been verified on FPGA.Using Verilog HDL hardware programming language,the algorithm partition module is simulated on ISE platform,and verified in Xilinx VC707 suite,which proves the feasibility and correctness of the TPA-SC algorithm.