Research On Performance And UIS Reliability Of SiC MOSFET Integrated Devices

In power electronic systems,power devices play an extremely important role.As a model of wide-bandgap semiconductor materials,SiC materials have excellent electrical properties,such as high critical electric field,high saturation electron drift speed and high thermal conductivity,which make SiC power devices emerge in the field of high-voltage and high-current applications.As a SiC material,SiC MOSFET mainly develops power devices.It has high switching speed and low switching loss.It is widely used in photovoltaic inverters,uninterruptible power supplies,and new energy vehicles.Integrating related diodes or sensors on MOSFET devices is also an important development direction.Since this type of device itself integrates the necessary devices in the system,the integrated device can not only improve the device performance but also reduce the system cost,so that the power electronic system can further reduce the area,increase the power density,and improve the integration of the system.The integration of Schottky diodes in SiC MOSFETs,namely JMOS,is a very typical integrated device.In JMOS,the Schottky diode is integrated next to the main device MOSFET.Due to the high frequency advantage of the Schottky diode,the dynamic loss of the body diode of the MOSFET device during switching is reduced,and the bipolar degradation of the body diode of the SiC MOSFET is reduced.Although JMOS exhibits excellent performance,its reliability still needs to be paid attention to.UIS(Unclamped Inductive Switching)capability is a measure of device robustness in unclamped stress switching,which demonstrates the device's resistance to failure and degradation in avalanche mode.Since the SiC MOSFET is smaller than the Si IGBT of the same voltage and current level in terms of device area,higher requirements are placed on the SiC MOSFET in terms of UIS capability.Therefore,it is necessary to understand the mechanism of device avalanche failure and degradation in order to further improve the device avalanche robustness.In this thesis,the basic structure,performance advantages,process flow and layout design of SiC JMOS are firstly introduced and analyzed,a SiC JMOS is designed,and the excellent characteristics of SiC JMOS are explained by Silvaco TCAD simulation,and the static parameters of SiC JMOS are tested.Then a UIS test platform was built to measure the single avalanche failure energy of SiC JMOS and conventional SiC MOSFET,and the degradation of JMOS under different avalanche energies of repetitive UIS.The avalanche electrothermal(AET)analytical model of JMOS during UIS is established by thermal diffusion equation to analyze the avalanche degradation and failure mechanism of JMOS.The model explains the limit temperature of SiC JMOS device failure and predicts the dynamic change of device temperature during UIS,which has certain guiding significance for studying the electrothermal behavior of SiC MOSFET devices during UIS.In a single UIS experiment,JMOS exhibits lower avalanche tolerance than conventional SiC MOSFETs.Through simulation and thermal model,it is found that the lattice temperature when the device fails reaches 1260 K,and through thermal analysis it is found that the temperature is mainly in the Schottky region.Combined with focused ion beam(FIB)slice analysis,the failure region is determined to be the Schottky region.The main reason is that during UIS,high temperature is generated inside the device,which causes electrothermal positive feedback in the Schottky region,and thermal runaway occurs,resulting in device burnout and failure.In the repetitive UIS experiment of JMOS,the degradation of SiC JMOS under different avalanche energies was measured.The simulation analysis and the Schottky barrier height measurement experiment show that the main reason for the degradation is that different avalanche energies produce different temperatures and affect the Schottky contact,making the The Schottky contact metal degrades,which affects the device breakdown voltage and the integrated Schottky diode turn-on drop.Finally,it is concluded that the Schottky barrier region is the key region that determines the avalanche robustness of SiC JMOS.