Research On Optimization And Prediction Method Of Routability In Digital Integrated Circuits

As the manufacturing process of the semiconductor continuously shrinks,the physical design of the chip is facing huge challenges.One of the notable features is increasingly stringent physical design rules,which will complicate chip routing and result in many routing-related problems.Although the existing electronic design automation(EDA)tools are constantly updated to keep up with the development of process nodes,there is still a lot of room for improvement in the quality of their routers,and their complex algorithm engine will cause a long design cycle.Therefore,the routability of the chip is of great significance to the physical design.The main work of this paper is to study the optimization and prediction methods of the routability in the chip's placement stage:(1)Congestion generated in the placement stage tends to increase the routing complexity,leading to a large number of design rule violations,which can visually reflect the routability of the placement.Therefore,this paper aims at the congestion in the placement and designs a local congestion elimination technique to optimize the routability of digital integrated circuits.The technique firstly selects the congested region with the highest congestion density through the method of local region expansion and merging.Then,based on two heuristic algorithms of simulated annealing(SA)and ant colony optimization(ACO),the optimal keepout margins being added around the high-pin cells in a specific congestion region are obtained to optimize the routing space.Experimental results show that compared with Synopsys ICC's internal congestion optimization algorithm,the proposed method can reduce design rule violations,short circuits and total wire length more effectively under the designs of different process nodes.(2)This paper has trained a deep learning model of graph neural network,which aims to predict the short circuits generated after detailed routing in advance in the placement stage,so that the designer can adjust the constraints according to the predicted results in time simply in the placement stage,which can greatly reduce the design iteration cycle.First,the features affecting the routability in each tile are extracted.Then,an adjacency matrix is built based on the connectivity of the tiles and a graph neural network Graph Sage is used to map local features of tiles to the corresponding adjacency matrix.Finally,the short circuits serve as labels to guide the model training.Compared with the existing literature,the model in this paper can achieve better prediction quality for designs with a higher number of short circuits.