Study And Application Of The Optimization Method For 1.2GHz Array Memory Physical Design

As an effective access storage structure, parallel memory is being widely accepted and used by designers. Considered the fact that physical design should be finished in the limited area overhead, while, parallel memory has many hard macros and large area overhead, which could cause the hard macro array placed closely, leading to local congestion, reducing the routability, affecting the design performance finally. Aiming at above problems, this paper under the background of physical design of 1.2GHz YHFT-DX DSP’s kernel Array Memory, starting with proventing detour and guarantee the design objective of GHz, studied the physical design process in integrated circuits intensively, put forward relevant optimization method and successfully applied in physical design in Array Memory. The main contents of this paper are as follows:1. The conventional placement rules of hard macros unable to meet the high utilization SRAM array layout. In this situation, this paper puts forward a method called HS to place hard macros. The experimental results show that HS method can get a good hard macros’ layout scheme in a short time with advantage of high utilization rate and global wirelength short, as well as strong operability. As for single BANK, in the case of approximate performance, the experimental result based on HS method compared to conventional method improved on 16% compressible layout area and the total signals wirelength can be shortened by 9%. HS method can reduce the impact of wirelength timing-delay on design performance effectively.2. For the matter that netlist synthesized by DC and DCT have worse routability and serious detour problem for limited layout resources in SRAM array physical design. This paper offered a circuit design method EULR, based on layout planning. EULR analysis layout under actual situation to select the specific circuit realization structure, reducing the number of interconnecting wire at maximum, extent to save routing resources. Compared the physical design results for netlists designed by above three methods, we find that netlists designed by EULR, whose total signal wirelength shortening 25% than DC synthesize, while 2% than DC T and the impact on GHz design objective significantly reduced.3. For the physical design tool ICC itself limitation, the design of SRAM array with the limit of layout routing resource, is not up to the standard for the reason of path delay caused by local detour. This paper come up with a routability driven placement algorithm MARP, basing on the forced derection, which avoid local detour and shorten path delay by compressing the interconnection wirelength between standard cells. Experimental results show that the result of global signal wirelength in BANK physical design based on MARP is 373,023 um, which is 93.5% achieved by ICC, while the critical path delay improved by 0.02 ns compared with the result achieved by ICC placed layout.4. Apply above optimization method in physical design with Array Memory: use HS to optimize SRAM array floorplan, use EULR to optimize SRAM array netlisit, use MARP to optimize SRAM array standard cells placement. In clock tree synthesis stage, we use positive clock skew to solve the problem of the critical path timing violations. Finally, we use static timing analysis tools Prime Time to analysis the performance of the design and we draw the conclusion that the array memory physical design based on above optimization methods could reach the design target of 1.2GHz in the typical process corner.