Research And Design Of Low-pass Filter With Adjustable Bandwidth In Wireless Communication Transceiver

The channel selection filter is an important unit in the transceiver system.Based on the requirements of broadband,multi-mode and mobilization of the new generation of wireless communication technology,this research designs and implements a low-power,multi-band adjustable CMOS fully integrated channel selection filter.Compared with passive filters,active filters can provide better filtering characteristics.With the development of integrated circuit technology,the integration of circuit systems has been continuously improved.In order to achieve good selection characteristics of the filter,we adopt an active form.The improvement of the filter's out-band suppression will increase its power consumption.Therefore,the goal of this research is to achieve high out-band suppression while ensuring low power consumption,and make the filter can be adjusted in multiple stages.Based on the background of this research and comparative analysis of mainstream design architecture,the Active-RC structure,which has excellent linearity,was selected as the structure of the filter for this design.In order to achieve flexible bandwidth tuning,a two-stage filter synthesis method is adopted.Each second-order unit is relatively independent of one another and can be individually tuned without mutual influence.The second-order unit uses the Sallen-Key topology.In order to reduce the influence of parasitic parameters,a coordinated tuning method of resistor array and capacitor array is used.In order to reduce the influence of non-ideal factors on the filter,an operational amplifier with high gain bandwidth product is designed.The gain-bandwidth product of the op amp is more than 13 times higher than the maximum cut-off bandwidth of the filter.The first stage of the OPA uses a cross-connected MOSFET as an active load.The second stage of the OPA uses a common source structure.The filter realized in a fully differential form.In terms of layout,the symmetry of the placement of differential devices is considered.The post-simulation result meets the design index.The channel selection filter designed is implemented based on 130 nm CMOS process.The supply voltage of the circuit is 1.2 V,the power consumption is 10.4 m W.The layout area is500×430?m²,the IIP₃ is 15.2 d Bm.The cut-off frequency of the filter can range within 4?60MHz with a step of 4 MHz.The fluctuation value in the band is below 1 d B.The filter fulfills the design requirements of multi-bands adjustable,high linearity,and low power consumption.