Research And Implementation Of Equalization Technology In 60GHz Millimeter Wave Communication System

60GHz Wireless communication technology is committed to solving high-speed,high-capacity,and low-latency data exchange scenarios.It has good international versatility and license-free attributes.It has wide available spectrum,large system capacity,and high transmission rate.It has better security,better anti-interference characteristics,high spectrum reusability,and small device size.Compared with the traditional wireless communication frequency band,the 60GHz millimeter wave has a path loss of 20dB?40dB higher,and it is easily blocked by people or other obstacles.Aiming at the communication in the 60GHz frequency band,it is planned to establish a communication test system with a single carrier architecture,and the data packet structure appropriately refers to IEEE 802.11ay.This article focuses on the research of the equalization algorithm in the system and deploys it on the hardware platform.Multi-path fading in the signal propaga-tion process will cause inter-symbol interference of the signal.Equalization is to offset the influence of the air channel on the transmitted signal,avoid distortion and inter-data interference so that the information can be transmitted correctly.Equalization can be divided into time-domain equalization and frequency-domain equalization from the realization domain.Considering the realization complexity of high-speed systems and the continuous development of digital processing hardware,this article only considers frequency domain e-qualization.Frequency domain equalization is divided into linear equalization and nonlinear equalization.The main difference is whether the output of the equalizer is used as feedback to re-enter the system.The first two chapters discussed the theoretical development of 60GHz wireless communication,stan-dard evolution,and the transmission model of the test system in this article.Two linear equalization algorithms are discussed in Chapter 3,namely Zero Forcing(ZF)and Linear Minimum Mean Square Error(LMMSE).Zero-forcing equalization eliminates inter-symbol interference to the maximum extent without considering noise,but at some frequency points with small gains,it will amplify noise and cause performance degradation.Linear minimum mean square error equalization adjusts the equalization coefficient according to the channel and noise information,so that the square mean of the difference between the detected signal and the trans-mitted signal through the equivalent system is minimized.Then this chapter discusses an iterative detection algorithm based on MMSE.The calculation process includes matrix inversion.The complexity of complex multiplication is on the order of O(N³);on this basis,a low complexity based on MMSE is proposed.The iterative detection algorithm avoids matrix inversion by assuming that the symbols in the data block have the same symbol variance so that the computational complexity is on the order of O(N log₂N).At the end of this chapter,we use the known sequence in the data block to use the interference cancellation algorithm to obtain a shorter transmission block to further reduce the equalization complexity.The above mentioned equalization algorithms can be used in combination with the interference cancellation algorithm,but due to the interference cancellation process It makes multiple superimposition of noise and is not suitable for linear algorithms,so we only consider combining it with a low-complexity iterative detection algorithm based on MMSE.Establish a simulation system to simulate the performance of the four algorithms of ZF,LMMSE,MMSE-based low-complexity iterative detection,and interference cancellation low-complexity iterative detection.The LMMSE algorithm has better performance than the ZF algorithm,and the low-complexity iterative detection algorithm based on MMSE is The overall performance is better than that of the linear equalization algorithm;the inter-ference cancellation low-complexity iterative detection algorithm has poor performance at low signal-to-noise ratios.the performance gradually increases as the signal-to-noise ratio improves.The iterative algorithm is very complicated to implement in FPGA hardware,so it is suitable to use the LMMSE algorithm for system implementation when resources are limited and the balance performance is good.In Chapter 4,we discussed the hardware module design of the 60GHz single-carrier wireless communi-cation system based on LMMSE equalization.The ADC sampling frequency is 2.4576GHz,and the FPGA operating frequency is 307.2MHz.The ADC uses the JESD204B protocol to transmit 8 continuous sampling point data to the FPGA each time.In order to meet the high-speed data processing requirements,8 parallel equalization links must be set to work at the same time.Three sub-modules are designed under the equaliza-tion module:1.Data reduction parallel module;2.Equalization sub-link module;3.Calculating equalization coefficient module.The data reduction parallel module is responsible for reorganizing and outputting high-speed data streams into 8 independent low-speed data streams,including 1 data reorganization logic module and 8 data cache modules.The equalization sub-link module is responsible for the equalization processing of low-speed data,including 1 FFT module,1 equalization calculation sub-module,and 1 IFFT module.The equalization coefficient calculation module is responsible for calculating and storing LMMSE equalization coefficients according to the time-domain channel and noise variance,including 1 FFT module,1 equalization coefficient calculation logic control sub-module,and 8 equalization coefficient buffer modules.At the end of this chapter,the implementation schemes of multiplication and division are compared at the maximum clock support level.Chapter 5 discusses the signal design of the equalization module and each sub-module and the meaning of each signal,and designs the corresponding waveform for each sub-module,that is,design the coupling relationship of the signals in the module.All modules are combined to form the hardware of the frequency domain equalization module in the 60GHz system.The equalization module was deployed and simulated on Altera's FPGA equipped with the S10 chip,and the simulation results of each module were consistent with the initial design.Finally,the maximum working clock supported by the equalization module is compared with the system required clock to meet the requirements,and various resource consumptions are given,which is in line with expectations.Chapter 6 discusses the summary of this article and the outlook for future work.