Fpga Design And Implementation Of The Single Carrier Equalizer In The Digital Terrestrial Television Transmission

GB20600-2006, the standard of the Chinese DTTB (digital terrestrial television broadcasting) has been promulgated on Aug.30, 2006. Single-carrier and OFDM are merged in this standard. And this standard characterizes by exellent system performance, high utilization ratio of frequency, strong flexibility and etc, capable of adapting to different applications in both urban and rural areas.The FPGA implementation of the equalizer for single-carrier of the standard has been completed in this thesis. This part is the important component of the receiver of single-carrier. Equalization in frequency domain and decision feedback in time domain is used for the single-carrier equalizer. The equalization in frequency domain is the feed-forward filtering of the DFE. And the traditional transversal filter is used in the feed-back filtering in time domain. After finishing the C program of the equalizer, the equalizer's performance has been validated by SPW4.8.2 simulation. The Verilog program has been designed based on the algorithm. And then, the function and timing simulations have been done by QuartusII. Finally, the hardware debugging on the hardware-platfom which is based on the Altera's Stratix series FPGA chip EP1S80B956C6FPGA has been done.In this dissertation, the develoing status of DTV all over the world is introduced firstly. And then the algorithm and the structure of the single-carrier equalization system as well as the related knowledge about FPGA design are introduced in Chapter 2. The simulation of the equalization system based on SPW4.8.2 is introduced in Chapter 3. The FPGA design and realization of the equalization system is introduced emphatically in Chapter 4. Additionally, the design of FFT of the PN based on FPGA is another part of the project and it is introduced in Chapter 5. Finally, this dissertation is summared in Chapter 6. The main work described in this thesis is listed as follows:1. Design the C program of the equalizer and finish simulation based on SPW4.8.2.2. Design the Verilog program of the equalizer and finish simulation based on Quartus II. 3. Debug the Verilog program of the equalizer on the hardware platform.4. Design the Verilog program of the FFT of the PN and finish simulation based on Quartus II.