Research On High Performance Computing Optimization Of Sparse Neural Network Based On Heterogeneous Platform

In recent years,the application of neural networks has become a research hotspot in the field of deep learning.With a complex structure,high-performance neural networks are required to reduce the amount of parameters and calculations through methods such as pruning.However,pruning destroys the regular distribution of network connections,which makes the hardware acceleration of sparse neural networks full of challenges.On the other hand,FPGA is playing an increasingly important role in the field of neural network hardware acceleration.The FPGAbased heterogeneous computing platform has broad application prospects.In order to realize the rapid deployment and high-performance reasoning of sparse neural networks on FPGA heterogeneous computing platforms,this thesis makes the following contributions:(1)A weight-oriented convolution kernel encoding method and a mask-based feature map encoding method is proposed.The improved COO coding method is adopted for the convolution kernel,which converts the convolution into element matrix multiplication to improve the performance of the accelerator.The mask-based compression method is adopted for the feature map to achieve higher compression efficiency while also realizing fast encoding into and decoding from the data stream.(2)A new sparse data stream is proposed.Streaming the input feature map to reduce power consumption and delay by increasing data multiplexing.Adjusting the arrangement order of feature map pixels reduces the size of the part and the buffer,and simplifies the encoding process after the calculation is completed.(3)Through a customizable computing accelerator design method and a design space exploration method based on machine learning and heuristic algorithms,the implementation and optimization of a high-performance sparse neural network accelerator based on a heterogeneous platform is completed.Use XGBoost-based machine learning methods to evaluate the optimized accelerator inference time,use heuristic algorithms based on simulated annealing for efficient exploration of complex design spaces,and perform efficient accelerator development and targeted optimization for different network models.Experimental results show that the method proposed in this thesis has a good acceleration effect on the forward inference calculation of sparse network on FPGA heterogeneous platform,and can achieve 241.8 GOP/s(for Alex Net),289.6 GOP/s(for VGG-16)and 324.8 GOP/s(for Res Net).Compared with the existing FPGA neural network accelerator,the acceleration effect is improved by 1.08×-21.59×,and the energy efficiency is improved by 1.02×-14.37×.