Termination Design And UIS Characteristic Research Of 100V UMOS

Power MOS devices are mainly composed of cell structure and termination structure,the latter is mainly used to alleviate the curvature effect caused by junction bending.The design of termination structure not only affects the voltage withstand performance of the whole device,but also strongly affects the dynamic avalanche characteristics of the device.Unclamped Inductive Switching(UIS)testing is an important method to evaluate the reliability of the device.Other researchers have completed the UIS simulation under the condition of parallel connection of MOS cells and termination structures,but there is still a lack of research on the detailed analysis of the dynamic avalanche process of the device in combination with temperature,current and other aspects.In this paper,the failure analysis of a 100V UMOS device based on actual tape-out data and test charts is carried out.Combined with the existing simulation experience and termination technology theory.The simulation and optimization of the Junction termination structure process conditions verify that the JTE’s constant temperature annealing time is insufficient so that impurities do not diffuse effectively and form a shallow junction whose impurity distribution is close to abrupt junctions.Under reverse bias condition,the termination impurities can not be effectively depleted,which leads to the low termination withstand voltage.This shows that the role of the JTE termination structure can also be explained by the linear graded junction principle besides the charge coupling principle.Under the existing process conditions,it is impossible to achieve 110V withstand voltage through JTE termination structure.At the same time,considering that the JTE termination structure under the process conditions can not be completely depleted,which is similar to the field limiting ring termination structure(FLR),we try to design the FLR termination to meet the design requirements.In the design of FLR termination structure,many factors such as ring spacing and main junction width are simulated and optimized.Based on the standard of lower and more uniform surface electric field and more uniform voltage distribution,a composite termination structure with three field limiting rings and a long field plate is designed.The breakdown voltage is about 111V,and the peak surface electric field is less than 2.0×10~5V/cm,which meets our design requirements.Finally,the UIS failure analysis of 100V UMOS cell is completed,and the improvement effect of increasing the base dose on avalanche performance is verified.In order to research the impact of the termination structure withstand voltage on the UIS characteristics of the whole device,a method of using the electrical parameters(voltage and current)and lattice temperature parameters obtained by simulation to study the dynamic avalanche process under the condition of the parallel connection of the UMOS cell and the termination structure is proposed.By changing the withstand voltage level of the termination structure,the dynamic avalanche process and UIS failure mechanism of the device under different termination withstand voltage levels are analyzed.It is proved that the avalanche performance of the device can be significantly improved by increasing the termination withstand voltage.The UIS failure analysis results of the device with 113V three field limiting ring termination structure show that the size of the active area will also significantly affect the avalanche performance of the device.The results of UIS simulation and analysis above provide a more detailed"internal view"for understanding the dynamic avalanche process of the device,and also provide a valuable reference for the reliability design of the device.