Exploration of mixed tunneling and avalanche breakdown effects on novel inductive design component

It is difficult to integrate inductors in Silicon RF CMOS circuits due to the substrate and other losses and large area consumptions. The p-n junction with/without drift region under avalanche or tunneling breakdown, however, will provide a natural inductive element. We will show, in this work, this junction inductor can indeed replace traditional spiral on-chip inductor in practical RF CMOS design. The analytical derivation shows that the noise generated by avalanche process can be mitigated by mixing tunneling into breakdown. In the first part of dissertation, a unified small-signal theory including avalanche, tunneling, and space charge effects is developed. Its equivalent circuit model is also derived and gives tremendous amount of insights on how much we can exploit avalanche and tunneling mechanisms by proper device design. One P-I-N inductor is designed. Silvaco simulation shows excellent agreement with our theory. To further reduce noise, the second two-region inductor design is proposed and verified by Silvaco simulations. In the second part of this dissertation, large signal theory is discussed and applied to inductor design. To further validate our theoretical work, a novel silicon PN junction inductor is fabricated based upon 2um silicon power bipolar process. Measured data is in excellent agreement with our theory. Inductance as high as 16uH is achieved.