Experimental Investigation Of The Single Pulse Avalanche Ruggedness Of SiC Power MOSFET

Semiconductor power devices are the core of the power electronics technology.Silicon carbide(SiC),with its high forbidden band width,high critical breakdown electric field strength and high thermal conductivity,makes SiC power devices more favorable for high-frequency,high-voltage and high-temperature applications,contributing to the improvement of efficiency and power density of power electronic systems.Among them,SiC MOSFET is a unipolar device with the insulated gate structure,and there is no trailing current in the turn-off process,which reduces the switching loss and thus the heat sink volume.Its high switching frequency is conducive to reducing the volume of inductors and capacitors in converters,increasing the power density of the device and effectively reducing the system cost.However,the ruggedness analysis of SiC MOSFETs under abnormal operations is not sufficient,and the analysis of its failure boundary and failure mechanism needs more data support.The avalanche is one of such abnormal operating conditions.When the device operates in the avalanche conduction,the drain-to-source voltage of the power MOSFET will reach the avalanche breakdown voltage.Such a high voltage conduction will cause the device junction temperature to rise rapidly,bringing the risk of failure to the device.Compared to conventional Si MOSFETs,the avalanche ruggedness of SiC MOSFETs are less described in the datasheets of current commercial SiC MOSFETs.In the avalanche ruggedness studies of SiC MOSFETs by domestic and international teams,the conclusion of device failure mechanism is inconsistent,and the comparison of the avalanche ruggedness of commercial SiC planar gate MOSFETs and trench gate MOSFETs is lacking.To address the above issues,this paper constructs a SiC MOSFET avalanche test platform to do the unclamped inductive switching(UIS)tests and carries out a two-stage study.First,this paper adopts a single pulse avalanche test scheme to study the avalanche ruggedness of the device through experiments.This paper specifies the failure boundary of the devices under test and compares the avalanche ruggedness of commercial SiC planar gate MOSFETs and trench gate MOSFETs.Secondly,this paper analyzes the single pulse avalanche failure mechanism of the devices under test and obtains the more reliable junction temperature estimation results by comparing the existing estimation methods,based on which a mathematical model is established to analyze whether the parasitic bipolar junction transistor of the device turns on or not.By comparing the avalanche ruggedness of the devices under different ambient temperatures and analyzing the failure spots after decapsulation of the failed devices,it is concluded that the causes of failure of the devices vary under different avalanche currents.In the case of higher avalanche currents,the device is inclined to fail prematurely due to the turn-on of the parasitic bipolar junction transistor.While in the case of lower avalanche currents,the device with more uniform cells fails due to metal melting caused by high junction temperatures.This paper provides important reference for device ruggedness evaluation and failure analysis.