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The Application Of Fibonacci Sequence Crosstalk Avoidance Coding And Decoding In High-speed Interconnection

Posted on:2022-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:W Y CaoFull Text:PDF
GTID:2518306725479444Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
As the circuit enters the deep sub-micron domain,the number of metal layers and stacked vias are increasing,and the wire spacing is decreasing.The coupling capacitance which can be neglect previously has now become an important part of the circuit.Coupling capacitance and crosstalk are always closely related.Their impact on the circuit can be divided into two aspects: delay and power consumption.Because of the existence of crosstalk,static signals will have logic information errors,and non-static signals will also experience timing changes.Specifically,signal glitches will increase,and the signal's rising and falling edge time will also change.These change will seriously affect the signal transmission.In this context,it is particularly important to propose anti-crosstalk technology in interconnection domain.Up to till now,crosstalk avoidance technology can be roughly divided into three categories: physical level technology,transistor level technology and register level technology.Among them,the physical level technology separates the interconnection lines from the physical level through spacer lines,shielded lines,and trunk lines,to achieve the purpose of reducing crosstalk.However,the physical level method requires a deep understanding of the electrical layout,and because of the introduction of new wiring,there will be a relatively large area overhead.In addition,the method of placing shielded wires cannot prevent the problem of simultaneous conversion in opposite directions.The transistor level technology is mainly to prevent the opposite conversion from occurring at the same time by tilting the signal conversion timing of adjacent wires.This method has the problem of area overhead and the timing problem of the transmitter and the receiver.Register-level technologies are mainly various encoding technologies,including error detection/correction codes,joint crosstalk avoidance and error correction codes and crosstalk avoidance coding.These coding methods can provide a good compromise between area and design cost,but the error detection and error correction codes and the joint crosstalk avoidance and error correction codes cannot completely ignore the crosstalk failure.Crosstalk avoidance coding can completely ignore high-level crosstalk,but many codes have non-linear problems,resulting in very complicated designs of the encoder and the decoder.Based on the Fibonacci digital system,this paper deeply researches and explores a linear crosstalk avoidance coding scheme,analyzes the characteristics of crosstalk avoidance coding without prohibition mode.According to this coding scheme,based on the Cadence design system,we proposed the corresponding codec hardware circuit structure,and then built the entire communication system for testing,added and studied the overall structure in detail,and analyzed the effect of coding methods under different channel conditions.This article first introduces the research background of crosstalk in the deep-micron domain,and then introduces the current research on anti-crosstalk technology.On this basis,we propose the crosstalk avoidance coding scheme used in our entire circuit,that is,crosstalk avoidance coding without prohibition mode.We designed the hardware structure of this kind of crosstalk avoidance coding,and finally carried out experimental test analysis.In the case of good channel conditions,the codec designed in this paper brings a30%-40% reduction jitter and an over 40% improvement in the signal-to-noise ratio in the victim channel.In the case that the channel condition itself is very bad,the codec designed in this paper will bring 20%-50% jitter reduction and different degrees of signal-to-noise ratio improvement for both the victim channel and aggressor channel.In summary,the codec designed in this paper is based on a linear algorithm and has a simple structure,which can effectively avoid undesirable transmission conditions,reduce crosstalk in the channel,increase the signal-to-noise ratio and reduce jitter of signal transmission,and finally improve transmission performance.
Keywords/Search Tags:high speed interconnection, fibonacci digital system, crosstalk avoidance codec, hardware structure
PDF Full Text Request
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