Design And Implementation Of Lightweight Block Cipher Reconfigurable Architecture

Lightweight block cipher algorithm is an important cornerstone to ensure the security of resource constrained devices.At present,the implementation methods mainly include hardware implementation based on ASIC and software implementation based on general processor.The former is difficult to meet the needs of different applications for the flexibility of encryption algorithm,and the latter is difficult to meet the needs of different applications for the high-performance implementation of encryption algorithm.Reconfigurable computing architecture has the advantages of high performance and flexibility,which provides a scientific and effective solution to the above problems.At present,there are few reconfigurable architectures for lightweight block cipher,while the reconfigurable architecture for traditional block cipher can also realize lightweight block cipher,but the implementation performance is not ideal.Aiming at this problem,this paper proposes a high-performance reconfigurable architecture for lightweight block cipher.Firstly,this paper analyzes 42 mainstream lightweight block cipher algorithms,and then extracts the operator characteristics of the algorithm;Then,the extracted pattern feature results and combined feature results are analyzed,and then the reconfigurable processing unit is designed;Next,according to the mapping law of lightweight block cipher algorithm,the reconfigurable processing unit array is designed,and then the overall architecture is designed.Next,by mapping PRESENT64/80 algorithm(typical lightweight block cipher algorithm based on SP network structure),SIMON64/128 algorithm(typical lightweight block cipher algorithm based on Feistel network structure)and SPECK64/128 algorithm(typical lightweight block cipher algorithm based on ARX structure)to the reconfigurable architecture designed in this paper,the utilization of reconfigurable units is obtained,the utilization of reconfigurable unit is compared with other reconfigurable cryptographic architectures.Finally,the functional simulation of PRESENT64/80algorithm,SIMON64/128 algorithm and SPECK64/128 algorithm is carried out.After the functional simulation,the logical synthesis is carried out to obtain the area efficiency,and the area efficiency is compared with other reconfigurable cryptographic architectures.The reconfigurable cryptographic architecture designed in this paper is implemented by TSMC 55 nm CMOS process.The operating frequency is up to 429MHz and the total area is 1.23 million equivalent gates(MGE).For different cryptographic algorithms,the area efficiency is up to 22.33 Gbit·s^-1·MGE^-1.Compared with other reconfigurable architectures that can realize lightweight block cipher,the utilization rate of reconfigurable unit is improved by 8.34%?18.94%,and the area efficiency is improved by 11.04%?7103.00%.