Research On FPGA-based Neural Network Binarization And Deployment Optimization

With the continuous development of deep learning,it plays an increasingly important role in the field of industrial.Deep Convolution Neural Networks(DCNN)is a key technology in the field of deep learning.Considering its excellent performance,it has been widely applied in image classification,target detection,dynamic tracking and so on.To meet the growing requirement,it is significant to design a real-time processing system with light weight,high accuracy and strong robustness.However,the reason why it is difficult to match the requirements of embedded applications is that deep convolutional neural networks usually takes up a lot of computing and storage resources.In order to solve the problem,the thesis designs a more light-weight neural network model and FPGA-based accelerator by improving the existing relevant researches.It can perform well on embedded devices with limited computing and storage resources and high demand for real-time performance.Among the existing network compression techniques,quantization based one serves as a promising and fast solution that yields highly compact models compared to their floatingpoint counterparts,by representing the network weights with very low precision.Along this direction,the thesis aims for different binarization algorithms to train the models by PyTorch.The network model of BinWideResNet is applied the algorithm of binarizing weights.In addition,the network model of XNOR-LeNet is applied the approach of XNOR-Net.It can achieve the purpose of effective to reduce the amount of calculation and the model size under the premise of model accuracy and robustness.In the process of building FPGA-based neural network accelerator,an valid analysis of the pre-trained model is necessary.Modular design is carried out through calculation subgraph.The data of feature map is based on shift selection to input.Furthermore,the ping-pong buffering mechanism and the pipeline processing mechanism is allowed to increase the utilization of resources.Using the HLS coding method,the inference acceleration of the binary neural network is realized on the FPGA.The results show that the classification accuracy of the XNOR-LeNet on the MNIST datasets is 97.47%.Compared with the origin network,the accuracy loss is barely 1.67%but the amount of calculation of its multiplication is reduced by 85%.In addition,the classification accuracy of the BinWideresNet on the CIFAR-10 datasets is 89.38%.Hence,it can meet the performance needs of embedded engineering applications.From what has been researched above,the parameters and calculation in model are obviously reduced.Consequently,it may draw the conclusion that this work of binarization neural network acceleration system owns important engineering significance in the future.