Low Power Cache Design Based On STT-RAM

The utilization of STT-RAM in embedded system and other modern advanced computers is deepening.STT-RAM has been used as the memory unit in main memory,as an alternative of DRAM,it can also be the substitute of SRAM at the Cache designing,which is very promising.The greatest advantage of STT-RAM is the leakage power of STT-RAM is lower than it of SRAM,because its non-volatility.Other advantages are higher density and good compatibility with CMOS technology.But there are some troubles like other non-volatile memory,such as more write energy and latency because of the non-volatility,and write life is smaller than SRAM,which make it difficult for STT-RAM to write at high speed.For different Cache layer,different design methods are used to balance the power and timing due to the asymmetry of the STT-RAM's write power and latency.Due to the different characteristic of STT-RAM and SRAM,the condition of applying the lower power design technology at SRAM and STT-RAM is different.Power gating on STT-RAM can save much design space of recovery and hold circuit,making the leakage power lower.On the other hand,this technology is hardly used on SRAM,because it spends too much time to recover the state,unless the data in SRAM is useless.Furthermore,the number of transistors in STT-RAM is less than that in SRAM,so the driving current is smaller than the current in SRAM,which can reduce the power-on time.For L1 Cache,because of the high frequency of operating,it isn't useful enough to use power gating technology.So,we don't research L1 Cache in this thesis.For L2 Cache,by recording the data of simulation running,and saving the Cache operating data,Cache model can satisfy the timing request.Establish an experiment,which contains the timing message about simulation beginning,ending time,write and read operation,combined with the model created by NVsim,it can get the dynamic power and leakage power of the L2 Cache model,and form the timing message.we can get the idle time of the case and do the power gating simulation.As the result,the STTRAM L2 Cache total power is about 10 percent of SRAM.But the Power Gating technology is not very useful,because the idle time is little and short,so the saving is about 1%.There are more memory units in L3 Cache than L2,but the timing request is less.It is easy to use STT-RAM in L3 Cache,and easy to use other lower power method because of the non-volatility.32MB memory size makes the lower leakage power advantage more obvious.Furthermore,the write and read operations are less than L1 and L2,and the leisure time is longer for L3 Cache.In simulation,the idle states contain tens of thousands of nanoseconds.So,the Power Gating is useful at L3 Cache.Compared with SRAM Cache,STT-RAM Cache can save about 95%leakage power.With Power Gating,another 10%leakage power can be saved,and Cache would not loss performance.