Based On FPGA To Design And Implement The Algorithm Of VGG-16 Neural Network

In recent years,the rapidly evolving Convolutional Neural Network has shown excellent classification and recognition ability in object detection,image classification,speech recognition and other application scenarios.With the deepening of network layers,the amount of storage and data computation continues to grow,the existing software implementation schemes are difficult to meet the requirements of Convolutional Neural Network for computing performance and power consumption.So it is necessary to study the hardware acceleration technology of CNN.In this thesis,by analyzing the characteristics of CNN algorithm model,a CNN hardware accelerator with excellent performance is studied and designed,which can effectively improve the computing performance of CNN through high parallelism.Based on the research of classical convolutional neural network algorithm.Firstly,this thesis studies the hardware acceleration design of convolution layer,analyzes the block loading mode of feature map and calculates the memory access times of block loading feature map,which provides a theoretical basis for analyzing the calculation scale of convolution layer.Secondly,the data reuse and parallel computing of convolution operation are studied.In the circuit computing,the input characteristic diagram and weight are reused by blocks,and a cache module is developed in the hardware to store the features,weight and calculation results,which reduces the number of memory access and power consumption;parallel computing is applied in the convolution window and between the input and output channels,the number of storage and computing resources used in different parallel schemes is analyzed to select the most trade-off design scheme for the hardware resources used.a multiplication and adder tree and a 6-stage pipeline are designed in the convolution acceleration module to improve computing performance.Finally,in the aspect of optimization design,the weight data is quantized,and the floating-point number is converted into 8-bit fixed-point number,which is conducive to data storage and calculation,and reduces the total amount of data transmission in off chip memory.In this thesis,VGG-16 is designed and implemented based on FPGA,and its software simulation and function verification are carried out.The power consumption of the hardware acceleration scheme designed in this thesisis 2.11 W at 100 MHz clock,and the peak computing power of the accelerator in convolution layer reaches 6.68 GOPS.The hardware acceleration circuit designed in this thesis achieves high peak computing power while meeting the requirements of low power consumption and low cost.